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Author

G. Dawe

Bio: G. Dawe is an academic researcher. The author has contributed to research in topics: Noise figure & CMOS. The author has an hindex of 1, co-authored 1 publications receiving 22 citations.

Papers
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Proceedings ArticleDOI
22 Jun 2008
TL;DR: It is shown that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance.
Abstract: In this paper, fundamental performance limits and scaling of a double-balanced passive mixer are examined. Analysis of the passive double-balanced mixer will show how its performance metrics are directly affected by the down-scaling of the transistor gate length, LG. We analyze the performance in terms of conversion gain (GC), 1-dB compression point (P1-dB) which we derive, and SSB Noise Figure (NF). We will show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance. This is verified through simulation and modeling results for mixers designed in CMOS 350 nm to 32 nm technology. We introduce a mixerpsilas figure-of-merit (FOMMIXER) to compare performance with technology scaling. Circuit designers and system architects can use this paper to find a suitable process technology that will meet their specifications.

24 citations


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Book ChapterDOI
01 Jan 2003
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

207 citations

Proceedings ArticleDOI
10 Jun 2018
TL;DR: A high-isolation fundamental mixer is used in which the matching networks are designed for good RF/IF isolation to simultaneously achieve high conversion gain and feasible module packaging to improve the signal-to-noise-and-distortion-ratio (SNDR) characteristics.
Abstract: This paper presents a 300-GHz transceiver based on 80-nm InP-HEMT technology. To improve the signal-to-noise-and-distortion-ratio (SNDR) characteristics, a high-isolation fundamental mixer is used in which the matching networks are designed for good RF/IF isolation to simultaneously achieve high conversion gain and feasible module packaging. The measured conversion gain of the fabricated mixer module is $-\mathbf{15}\pm \mathbf{2\ dB}$ , where the LO frequency, IF, and RF are 270, 2–32, and 272–302 GHz. The 300-GHz transceiver consists of the high-isolation mixer, 300-GHz amplifiers, and commercially available frequency multipliers as the LO source. It achieves 100-Gb/s wireless data transmission using 16QAM over a distance of 2.22 m with a 50-dBi antenna. To the best of the authors' knowledge, this is the highest wireless data rate ever achieved using only electronic devices.

88 citations

Journal ArticleDOI
TL;DR: A 300-GHz-band 120-Gb/s wireless transceiver front-ends (TRX) using the in-house InP-based high-electron-mobility-transistor (InP-HEMT) technology for beyond-5G is developed.
Abstract: We developed a 300-GHz-band 120-Gb/s wireless transceiver front-ends (TRX) using our in-house InP-based high-electron-mobility-transistor (InP-HEMT) technology for beyond-5G. The TRX is composed of the RF power amplifiers (PAs), mixers, and local oscillation (LO) PAs which are all packaged in individual waveguide (WG) modules by using a ridge coupler for low-loss WG-to-IC transition. RF PAs are designed using the low-impedance inter-stage-matching technique to reduce the inter-stage matching loss of the amplifier stages, and the back-side DC line (BDCL) technique is used to simplify the layout and to improve the gain of the PAs. The fabricated RF PAs show a high output 1-dB compression point of more than 6 dBm from 278 to 302 GHz. The mixers are used for both up- and down-conversion in the transmitter and receiver. These mixers are designed to have high conversion gain (CG) over the wideband even after packaging by enhancing the isolation between the RF and IF ports. The measured CG of mixer module is −15 dB, and the 3-dB IF-bandwidth is 32 GHz. The LO PAs are also designed using the BDCL technique so that they can supply the required LO power to the mixers. The TRX with these InP building blocks enables the data transmission of a 120 Gb/s 16QAM signal over a link distance of 9.8 m.

87 citations

Journal ArticleDOI
TL;DR: In this article, a SiGe BiCMOS reflectometer for 0.01-26 GHz two-port vector network analyzers (VNAs) is presented, which is composed of a resistive bridge coupler and two wideband heterodyne receivers for coherent magnitude and phase detection.
Abstract: This article presents a packaged SiGe BiCMOS reflectometer for 0.01–26-GHz two-port vector network analyzers (VNAs). The reflectometer chip is composed of a resistive bridge coupler and two wideband heterodyne receivers for coherent magnitude and phase detection. In addition, a high-linearity receiver channel is designed to accommodate ~20 dBm of RF input power to the reflectometer. External sources are used to provide stimulus over the entire bandwidth, and a high-linearity shunt 50- $\Omega $ switch is placed at the input of each reflectometer chip to provide a matched condition for better measurement accuracy. The measured dynamic range (DR) of the heterodyne receiver is 129±3 dB at 0.01–26 GHz at an IF resolution bandwidth (RBW) of 10 Hz. The reflectometer chip is packaged on a low-cost printed circuit board (PCB) and connectorized for repeatable measurements. Several passive and active device-under-test (DUTs), such as filters and amplifiers, are measured in single- and dual-port complex $S$ -parameter setup at 0.01–26 GHz. The single-chip reflectometer results in excellent agreement with commercially available test equipment and with minimal magnitude and phase difference. Several definitions (mean deviation and error vector) are used to quantify the measurement accuracy. A measured $S_{21}$ of −80 dB is obtained using high-rejection filters. An in-depth DR analysis of possible limiting factors in the measurement setup is also presented. This article shows that silicon-based highly integrated reflectometers can be used in low-cost VNAs with excellent DR and accuracy.

12 citations

Journal ArticleDOI
TL;DR: A system of radio-triggered batteryless monolithic wireless sensor based on mm-wave wireless power transfer technique is introduced in this work, and the sensitivity of the receiver is improved by applying the IJLO into the self-mixing architecture.
Abstract: With the growing attention at 60 GHz ISM band on millimeter-wave therapy for diseases treatment of sedative, anti-inflammatory actions or immune system stimulation, growing demand for new biomedical monitoring and treating systems with more bandwidth, high data rates and low power creates new challenges for 60 GHz body area network. Most smart wireless sensors wireless sensing operates on battery, which limits their life-time. To overcome this limitation, a system of radio-triggered batteryless monolithic wireless sensor based on mm-wave wireless power transfer technique is introduced in this work. From the system power budget analysis, it could support 10 bits communication within 10 cm, which would be sufficient for mm-wave wireless sensing application. Furthermore, it is identified that the receiver is power limited. Based on the system evaluation, an injection locked oscillator based self-mixing receiver is presented. In this architecture, the IJLO based LO scheme is used to save receiver power consumption. The sensitivity of the receiver is improved by applying the IJLO into the self-mixing architecture. This single chip receiver is implemented in a 65 nm CMOS technology. The DC power consumption of this receiver is only 16.4 mA from 1 V power supply. This power consumption is lower than other mm-wave receivers, which is an important step towards fully integrated monolithic sensor nodes.

11 citations