G
G. De Micheli
Researcher at École Normale Supérieure
Publications - 25
Citations - 871
G. De Micheli is an academic researcher from École Normale Supérieure. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 16, co-authored 25 publications receiving 815 citations. Previous affiliations of G. De Micheli include École Polytechnique.
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Energy Harvesting and Remote Powering for Implantable Biosensors
TL;DR: In this paper, a review of the most popular techniques to harvest energy for implantable biosensors is presented, focusing on the inductive links that are able to deliver power wirelessly through the biological tissues and enable bidirectional data communication with the implanted sensors.
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An Efficient Gate Library for Ambipolar CNTFET Logic
TL;DR: A library of static ambipolar carbon nanotube field effect transistor (CNTFET) gates based on generalized NOR-NAND-AOI-OAI primitives, which efficiently implements XOR-based functions are proposed, which results in ambipolar gates with a higher expressive power than conventional complementary metal-oxidesemiconductor (CMOS) libraries.
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Thermal Balancing Policy for Multiprocessor Stream Computing Platforms
TL;DR: The design of a lightweight thermal balancing policy MiGra, which bounds on-chip temperature gradients via task migration, is presented, which achieves significantly better thermal balancing than state-of-the-art thermal management solutions while keeping the number of migrations bounded.
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Processor Speed Control With Thermal Constraints
TL;DR: It is shown that the problem of processor speed control subject to thermal constraints for the environment is a convex optimization problem, and an efficient infeasible-start primal-dual interior-point method for solving the problem is presented.
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Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs
Pierre-Emmanuel Gaillardon,Davide Sacchetto,Giovanni Betti Beneventi,M. Haykel Ben Jamaa,L. Perniola,Fabien Clermidy,Ian O'Connor,G. De Micheli +7 more
TL;DR: This paper introduces a novel set of building blocks for field-programmable gate arrays (FPGAs) using eNVMs, proposing an eNVM-based configuration point, a look-up table structure with reduced programming complexity and a high-performance switchbox arrangement.