G. P. Biswas

Bio: G. P. Biswas is an academic researcher from Indian Institute of Technology Dhanbad. The author has an hindex of 1, co-authored 1 publications receiving 2 citations.

Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs

Abstract: In 3D IC, wrapper chains can span across vertical directions which causes the increase in number of TSVs(through-silicon-vias)(which is used to interconnect different cores in the vertical directions). Excessive use of TSVs in wrapper design causes routing congestion and additional overhead in manufacturing. Therefore, optimization of wrapper length and judicious use of TSVs are the focus of 3D wrapper architecture design. In this work, we first propose a heuristic procedure to determine the placement of wrapper elements in several layers of 3D SOC for a number of wrapper chains and interconnect them using available number of TSVs such that the length of the longest wrapper length (LWL) is minimized. Then we apply particle swarm optimization (PSO) based metaheuristic approach on the results obtained in first case to determine the placement of wrapper chains and interconnect them using minimum number of TSVs such that the length of LWL is minimized. We compare our results with earlier works and the experimental results show the efficacy of our algorithm.

Designing balanced wrapper chains in 3D SoC under constrained TSVs

Abstract: Three-dimensional integrated circuit (3D-IC) has emerged as a savior of failing Moore’s law, where reduced length of interconnects is guaranteed with some added advantages like heterogeneous integration, higher computation per volume, etc. These benefits are also exhibited in 3D SoCs (3D System on Chips) to use the already built cores. However, testing these large complex SoCs in lesser time has become a challenge. In this work, we propose a simulated annealing-based wrapper chain design algorithm that will balance the length of the wrapper chain. The number of TSVs (Through Silicon Vias) is also kept as a constraint so that the number of TSVs could also be reduced. Rigorous experiments were conducted on several ITC’02 SoC benchmark and the results when compared with a recent work which showed that our proposed approach recorded better test lengths in more than 90% cases with an average reduction of 6.42% in test length. Our algorithms also used less number of TSVs in approximately 90% of the cases with an average reduction of 23.82% in the number of TSVs, in comparable CPU time.

Effects of 60Co γ ray radiation on the transmission characteristics of interconnection structures for 3D packaging

Abstract: Purpose Concerning the radiation effects on the three-dimensional (3D) packaging in space environment, this study aims to investigate the influence of the total dose effect on the transmission characteristics of high-frequency electrical signals using experimental and simulation methods. Design/methodology/approach This work carries out the irradiation test of the specimens and measures their S21 parameters before and after irradiation. A simulation model describing the total dose effect was built based on the experimental test results. And, the radiation hardening design is evaluated by the simulation method. Findings The experimental results demonstrate that the S21 curve of the interconnection decreases with the increase of the irradiation dose, indicating that the total dose effect leads to the decline of its signal transmission characteristics. According to the simulation results, decreasing the height of the through silicon via (TSV), increasing the radius of the TSV, reducing the length of Si and increasing the number of grounded through silicon via have positive effects on improving the radiation resistance of the interconnection structure. Originality/value This work investigates the effect of radiation on the transmission characteristics of interconnection structures for 3D packaging and proposes the hardening design methods. It is meaningful for improving the reliability of 3D packaging in space applications.