G. Patounakis

Bio: G. Patounakis is an academic researcher from Columbia University. The author has contributed to research in topics: Asynchronous communication & Fluorescence spectroscopy. The author has an hindex of 9, co-authored 9 publications receiving 475 citations.

A fully integrated on-chip DC-DC conversion and power management system

Abstract: It is widely recognized that adaptive control of the power supply is one of the most effective variables to achieve energy-efficient computation. Most on-chip dc-dc conversion systems have relied on buck converters with off-chip LC filters. In this paper, we describe the development of a software controllable, fully integrated on-chip dc-dc downconversion system that combines switched-capacitor voltage dividers and linear regulators to efficiently regulate from 2.5 V down to about 0.65 V. The use of switched-capacitor supplies offers better efficiencies than what is achievable with linear regulators alone.

Pulsed current-mode signaling for nearly speed-of-light intrachip communication

Abstract: In this paper, we describe the design of on-chip repeater-less interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8-Gb/s serial link employing this pulsed current-mode signaling in a 0.18-/spl mu/m CMOS process is described and measured.

Active CMOS biosensor chip for fluorescent-based detection

Abstract: An active CMOS biosensor chip for fluorescent-based detection is provided that enables time-gated, time-resolved fluorescence spectroscopy. In one embodiment, analytes are loaded with fluorophores that are bound to probe molecules immobilized on the surface of the chip. Photodiodes and other circuitry in the chip are used to measure the fluorescent intensity of the fluorophore at different times. These measurements are then averaged to generate a representation of the transient fluorescent decay response unique to the fluorophores. In addition to its low-cost, compact form, the biosensor chip provides capabilities beyond those of macroscopic instrumentation by enabling time-gated operation for background rejection, easing requirements on optical filters, and by characterizing fluorescence lifetime, allowing for a more detailed characterization of fluorophore labels and their environment. The biosensor chip can be used for a variety of applications including biological, medical, in-the-field applications, and fluorescent lifetime imaging applications.

Near speed-of-light on-chip interconnects using pulsed current-mode signalling

Abstract: In this paper, we describe the design of on-chip repeaterless interconnects with nearly speed-of-light latency. Sharp current-pulse data transmission is used to modulate transmitter energy to higher frequencies, where the effect of wire inductance is maximized, allowing the on-chip wires to function as transmission lines with considerably reduced dispersion. A prototype 8 Gbps serial link employing this pulsed current-mode signalling in a 0.18 /spl mu/m CMOS process is described and measured.

Active CMOS Array Sensor for Time-Resolved Fluorescence Detection

Abstract: Surface-based sensing assays based on fluorescence-based detection have become commonplace for both environmental and biomedical diagnostics. Traditional array scanners are expensive, large, and complex instruments. This paper describes the design of an active CMOS biosensor substrate for fluorescence-based assays that enables time-gated, time-resolved fluorescence spectroscopy without the need for an external reader. The array is sensitive to photon densities as low as 1.15times108/cm2, has a dynamic range of over 74 dB, and has subnanosecond timing resolution. Sensitivity is achieved through subsampling and averaging

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

Abstract: To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Full On-Chip CMOS Low-Dropout Voltage Regulator

Abstract: This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.

Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters

Abstract: This paper describes design techniques to maximize the efficiency and power density of fully integrated switched-capacitor (SC) DC-DC converters. Circuit design methods are proposed to enable simplified gate drivers while supporting multiple topologies (and hence output voltages). These methods are verified by a proof-of-concept converter prototype implemented in 0.374 mm2 of a 32 nm SOI process. The 32-phase interleaved converter can be configured into three topologies to support output voltages of 0.5 V-1.2 V from a 2 V input supply, and achieves 79.76% efficiency at an output power density of 0.86 W/mm2 .

Flattened Butterfly Topology for On-Chip Networks

Abstract: With the trend towards increasing number of cores in chip multiprocessors, the on-chip interconnect that connects the cores needs to scale efficiently. In this work, we propose the use of high-radix networks in on-chip interconnection net- works and describe how the flattened butterfly topology can be mapped to on-chip networks. By using high-radix routers to reduce the diameter of the network, the flattened butterfly offers lower latency and energy consumption than conven- tional on-chip topologies. In addition, by exploiting the two dimensional planar VLSI layout, the on-chip flattened but- terfly can exploit the bypass channels such that non-minimal routing can be used with minimal impact on latency and en- ergy consumption. We evaluate the flattened butterfly and compare it to alternate on-chip topologies using synthetic traffic patterns and traces and show that the flattened but- terfly can increase throughput by up to 50% compared to a concentrated mesh and reduce latency by 28% while re- ducing the power consumption by 38% compared to a mesh network.

Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems

Abstract: Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising solution for designing the interconnect fabric of multicore SoCs. But the performance requirements of NoC infrastructures in future technology nodes cannot be met by relying only on material innovation with traditional scaling. The continuing demand for low-power and high-speed interconnects with technology scaling necessitates looking beyond the conventional planar metal/dielectric-based interconnect infrastructures. Among different possible alternatives, the on-chip wireless communication network is envisioned as a revolutionary methodology, capable of bringing significant performance gains for multicore SoCs. Wireless NoCs (WiNoCs) can be designed by using miniaturized on-chip antennas as an enabling technology. In this paper, we present design methodologies and technology requirements for scalable WiNoC architectures and evaluate their performance. It is demonstrated that WiNoCs outperform their wired counterparts in terms of network throughput and latency, and that energy dissipation improves by orders of magnitude. The performance of the proposed WiNoC is evaluated in presence of various traffic patterns and also compared with other emerging alternative NoCs.