Visible-light-driven photochemistry has continued to attract heightened interest due to its capacity to efficiently harvest solar energy and its potential to solve the global energy crisis. Plasmonic nanostructures boast broadly tunable optical properties coupled with catalytically active surfaces that offer a unique opportunity for solar photochemistry. Resonant optical excitation of surface plasmons produces energetic hot electrons that can be collected to facilitate chemical reactions. This review sums up recent theoretical and experimental approaches for understanding the underlying photophysical processes in hot electron generation and discusses various electron-transfer models on both plasmonic metal nanostructures and plasmonic metal/semiconductor heterostructures. Following that are highlights of recent examples of plasmon-driven hot electron photochemical reactions within the context of both cases. The review concludes with a discussion about the remaining challenges in the field and future oppor...

Surface-Plasmon-Driven Hot Electron Photochemistry

This article reviews several classes of inorganic semiconductor materials that can be used to form high-performance thin-film transistors (TFTs) for large area, flexible electronics. Examples ranging from thin films of various forms of silicon to nanoparticles and nanowires of compound semiconductors are presented, with an emphasis on methods of depositing and integrating thin films of these materials into devices. Performance characteristics, including both electrical and mechanical behavior, for isolated transistors as well as circuits with various levels of complexity are reviewed. Collectively, the results suggest that flexible or printable inorganic materials may be attractive for a range of applications not only in flexible but also in large-area electronics, from existing devices such as flat-panel displays to more challenging (in terms of both cost and performance requirements) systems such as large area radiofrequency communication devices, structural health monitors, and conformal X-ray imagers.

Inorganic semiconductors for flexible electronics

Semiconductor nanowires (NWs) have been studied extensively for over two decades for their novel electronic, photonic, thermal, electrochemical and mechanical properties. This comprehensive review article summarizes major advances in the synthesis, characterization, and application of these materials in the past decade. Developments in the understanding of the fundamental principles of "bottom-up" growth mechanisms are presented, with an emphasis on rational control of the morphology, stoichiometry, and crystal structure of the materials. This is followed by a discussion of the application of nanowires in i) electronic, ii) sensor, iii) photonic, iv) thermoelectric, v) photovoltaic, vi) photoelectrochemical, vii) battery, viii) mechanical, and ix) biological applications. Throughout the discussion, a detailed explanation of the unique properties associated with the one-dimensional nanowire geometry will be presented, and the benefits of these properties for the various applications will be highlighted. The review concludes with a brief perspective on future research directions, and remaining barriers which must be overcome for the successful commercial application of these technologies.

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25th Anniversary Article: Semiconductor Nanowires – Synthesis, Characterization, and Applications

With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions.

https://iopscience.iop.org/article/10.1088/0268-1242/31/6/063002/pdf

Resistive switching memories based on metal oxides: mechanisms, reliability and scaling

This paper reviews the present knowledge on tantalum pentoxide (Ta 2 O 5 ) thin films and their applications in the field of microelectronics and integrated microtechnologies. Different methods used to produce tantalum oxide layers are described, emphazing elaboration mechanisms and key parameters for each technique. We also review recent advances in the deposition of Ta 2 O 5 in the particular field of microelectronics where high quality layers are required from the structural and electrical points of view. The physical, structural, optical, chemical and electrical properties of tantalum oxide thin films on semiconductors are then presented and essential film parameters, such as optical index, film density or dielectric permittivity, are discussed. After a reminder of the basic mechanisms that control the bulk electrical conduction in insulating films, we carefully examine the origin of leakage currents in Ta 2 O 5 and present the state-of-the-art concerning the insulating behaviour of tantalum oxide layers. Finally, applications of tantalum oxide thin films are presented in the last part of this paper. We show how Ta 2 O 5 has been employed as an antireflection coating, insulating layer, gate oxide, corrosion resistant material, and sensitive layer in a wide variety of components, circuits and sensors.

Tantalum pentoxide (Ta2O5) thin films for advanced dielectric applications

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

In this letter, a significantly improved uniformity of device parameters (for cycle-to-cycle uniformity within one device and device-to-device uniformity), such as set voltage, reset voltage, and HRS and LRS resistance distributions, is successfully demonstrated on HfOx/TiOx multilayer (ML)-based resistive switching devices, as compared with HfOx-based single-layer device. In addition, the reported ML devices are free from forming process, which is greatly beneficial from the viewpoint of RRAM circuit operation. It is believed that both the Ti doping effect and the confinement of conduction filament within different dielectrics layers contribute to the improvement.

$\hbox{HfO}_{x}/\hbox{TiO}_{x}/\hbox{HfO}_{x}/ \hbox{TiO}_{x}$ Multilayer-Based Forming-Free RRAM Devices With Excellent Uniformity

We design and experimentally demonstrate an ultrashort integrated polarization splitter on silicon-on-insulator (SOI) platform. Our polarization splitter uses a hybrid plasmonic waveguide as the middle waveguide in a three-core arrangement to achieve large birefringence, allowing only transverse-magnetic (TM) polarized light to directionally couple to the cross port of the directional coupler. Finite-difference time-domain (FDTD) and eigenmode expansive (EME) calculations show that the splitter can achieve an extinction ratio of greater than 15 dB with less than 0.5 dB insertion losses. The polarization splitter was fabricated on SOI platform using standard complementary metal-oxide-semiconductor (CMOS) technology and measured at telecommunications wavelengths. Extinction ratios of 12.3 dB and 13.9 dB for the transverse-electric (TE) and TM polarizations were obtained, together with insertion losses of 2.8 dB and 6.0 dB.

CMOS compatible polarization splitter using hybrid plasmonic waveguide.

Horizontal metal/insulator/Si/insulator/metal nanoplasmonic slot waveguide (PWG), which is inserted in a conventional Si wire waveguide, is fabricated using the standard Si-CMOS technology. A thin insulator between the metal and the Si core plays a key role: it not only increases the propagation distance as the theoretical prediction, but also prevents metal diffusion and/or metal-Si reaction. Cu-PWGs with the Si core width of ~134–21 nm and ~12-nm-thick SiO2 on each side exhibit a relatively low propagation loss of ~0.37–0.63 dB/µm around the telecommunication wavelength of 1550 nm, which is ~2.6 times smaller than the Al-counterparts. A simple tapered coupler can provide an effective coupling between the PWG and the conventional Si wire waveguide. The coupling efficiency as high as ~0.1–0.4 dB per facet is measured. The PWG allows a sharp bending. The pure bending loss of a Cu-PWG direct 90° bend is measured to be ~0.6–1.0 dB. These results indicate the potential for seamless integration of various functional nanoplasmonic devices in existing Si electronic photonic integrated circuits (Si-EPICs).

Silicon-based horizontal nanoplasmonic slot waveguides for on-chip integration

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around nand p-FETs, fabricated using these stacked NW arrays as the channel (Lgges0.35 mum), exhibit excellent device performance with high ION/IOFF ratio (~106), near ideal subthreshold slope (~62-75 mV/dec) and low drain induced barrier-lowering (~20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate

G. Q. Lo

Papers

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

$\hbox{HfO}_{x}/\hbox{TiO}_{x}/\hbox{HfO}_{x}/ \hbox{TiO}_{x}$ Multilayer-Based Forming-Free RRAM Devices With Excellent Uniformity

CMOS compatible polarization splitter using hybrid plasmonic waveguide.

Silicon-based horizontal nanoplasmonic slot waveguides for on-chip integration

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors