Biological cells are characterized by highly complex phenomena and processes that are, to a great extent, interdependent. To gain detailed insights, devices designed to study cellular phenomena need to enable tracking and manipulation of multiple cell parameters in parallel; they have to provide high signal quality and high-spatiotemporal resolution. To this end, we have developed a CMOS-based microelectrode array system for in vitro applications that integrates six measurement and stimulation functions, the largest number to date. Moreover, the system features the largest active electrode array area to date ( $4.48 \times 2.43$ mm2) to accommodate 59 760 electrodes, while its power consumption, noise characteristics, and spatial resolution (13.5- $\mu$ m electrode pitch) are comparable to the best state-of-the-art devices. The system includes: 2048 action potential (AP, bandwidth: 300 Hz–10 kHz) recording units, 32 local-field-potential (LFP, bandwidth: 1 Hz–300 Hz) recording units, 32 current recording units, 32 impedance measurement units, and 28 neurotransmitter detection units, in addition to the 16 dual-mode voltage-only or current/voltage-controlled stimulation units. The electrode array architecture is based on a switch matrix, which allows for connecting any measurement/stimulation unit to any electrode in the array and for performing different measurement/stimulation functions in parallel.

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In Vitro Multi-Functional Microelectrode Array Featuring 59 760 Electrodes, 2048 Electrophysiology Channels, Stimulation, Impedance Measurement, and Neurotransmitter Detection Channels

A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm2 chip was fabricated in a standard 0.16 μm CMOS process.

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A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset

This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 muVRMS), the DC offset 2 muV, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 muA current during conversion

/pdf/a-low-power-22-bit-incremental-adc-4quii4y1ly.pdf

A low-power 22-bit incremental ADC

A calibration-free, high-resolution analog-to-digital converter designed for a bioluminescence sensor array employs incremental sigma-delta (ΣΔ) modulation to combine the advantages of oversampling with an input multiplexing capability. The resolution of incremental ΣΔ modulators can be improved significantly by means of a technique similar to extended counting. In the approach proposed in this paper, analog-to-digital conversion is accomplished with a two-step process in which the residual error from a second-order incremental ΣΔ modulator is encoded using a successive approximation ADC. By this means it is possible to achieve enhanced resolution and improved static linearity while maintaining a one-to-one mapping between individual input and output samples. An experimental implementation of the proposed modulator has been integrated in a 0.18-μm CMOS technology. Operating from a 1.8-V supply, it achieves a dynamic range of 90.1 dB and a peak signal-to-noise and distortion ratio (SNDR) of 86.3 dB at a conversion rate of 1 MSample/s, with 38.1-mW power consumption.

A High-Resolution Low-Power Incremental $\Sigma\Delta$ ADC With Extended Range for Biosensor Arrays

This paper presents a 20-b read-out IC with ±40-mV full-scale range that is intended for use with bridge transducers. It consists of a current-feedback instrumentation amplifier (CFIA) followed by a switched-capacitor incremental ΔΣ ADC. The CFIA's offset and 1/f noise are mitigated by chopping, while its gain accuracy and gain drift are improved by applying dynamic element matching to its input and feedback transconductors. Their mismatch is reduced by a digitally assisted correction loop, which further reduces the CFIA's gain drift. Finally, bulk-biasing and impedance-balancing techniques are used to reduce the common-mode dependency of these transconductors, which would otherwise limit the achievable gain accuracy. The combination of these techniques enables the read-out IC to achieve 140-dB CMRR, a worst-case gain error of 0.04% over a 0-2.5 V common-mode range, a maximum gain drift of 0.7 ppm/°C and an INL of 5 ppm. After applying nested-chopping, the read-out IC achieves 50-nV offset, 6-nV/°C offset drift, a thermal noise floor of 16.2 nV/√Hz and a 0.1-mHz 1/f noise corner. Implemented in a 0.7-μm CMOS technology, the prototype read-out IC consumes 270 μA from a 5-V supply.

/pdf/a-20-b-pm-40-mv-range-read-out-ic-with-50-nv-offset-and-0-04-2bg0pa1pyc.pdf

A 20-b $\pm$ 40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for Bridge Transducers

A sigma-delta modulator has a chopper voltage reference providing a reference signal having a clock dependent offset voltage, a single-bit or a multi-bit digital-to-analog converter (DAC); a plurality of capacitor pairs; a plurality of switches to couple any capacitor pair to an input or reference signal; and a control unit controlling sampling through said switches to perform a charge transfer in two phases wherein any capacitor pair can be selected to be assigned to the input or reference signal, wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically, and wherein a DAC output value and a reference offset state define switching sequences wherein each switching sequence independently rotates said capacitor pairs and wherein at least one switching sequence is selected depending on a current DAC output value and a current reference offset state.

2-phase gain calibration and scaling scheme for switched capacitor sigma-delta modulator using a chopper voltage reference

A digital decimation filter with programmable frequency notches is disclosed. The digital decimation filter performs integration, differentiation, and scaling to produce a filtered output signal. The differentiation is preformed by a programmable counter. The filter has a control unit that controls the behavior of the filter. The control unit has registers to contain ther values of the frequency notches of the filter. The control unit activates the differentiator based on the value of the frequency notches in order to achieve filtration. The scaling unit uses a register, a bit shifter, and an adder to minimize complexity. The digital decimation filter provides high rejection with low complexity.

Digital decimation filter

A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.

Main clock high precision oscillator

A low power 22bit incremental ADC, including an on-chip digital filter and a low noise/low drift oscillator, was realized in a 0.6-/spl mu/m CMOS process. It incorporates a novel offset cancellation scheme based on fractal sequences, a novel high accuracy gain control circuit, and a novel reduced complexity realization for the on chip sine filter. The measured output noise was 0.28 ppm (2.8 /spl mu/V/sub RMS/), the dc offset 2 /spl mu/V, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 125 /spl mu/A current during conversion.

Gabriele Bellini

Papers

A low-power 22-bit incremental ADC

2-phase gain calibration and scaling scheme for switched capacitor sigma-delta modulator using a chopper voltage reference

Digital decimation filter

Main clock high precision oscillator

A low-power 22-bit incremental ADC with 4 ppm INL, 2 ppm gain error and 2 /spl mu/V DC offset