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Gaetano Bazzano

Bio: Gaetano Bazzano is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Power semiconductor device & Power MOSFET. The author has an hindex of 9, co-authored 27 publications receiving 201 citations.

Papers
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Journal ArticleDOI
TL;DR: The implementation of a devised flow to generate the layer-based electrothermal PSpice model of an IPEM and the simulation flow of the model are described and the results are compared with a commercial finite-element-based package used as a benchmark.
Abstract: Integrated power electronics modules (IPEMs) represent an innovative typology of power electronics assemblies able to guarantee several advantages such as increasing of power density, better management of the thermal flows, and a significant reduction of the package sizes. Their characteristics make them suitable for applications like motor drives or power conditioning. IPEM usage in emerging fields like hybrid automotive traction and electric generation from renewable energy sources is continuously increasing. In this paper, we describe the implementation of a devised flow to generate the layer-based electrothermal PSpice model of an IPEM and the simulation flow of the model. The proposed modeling methodology allows reducing an electrothermal multidomain problem to an electrical single one. The general PSpice-like nature of the proposed model makes it suitable for a wide range of simulation frameworks where the integration of heterogeneous multiphysics models could be a difficult task. The outlining of both electrical and thermal PSpice layers is discussed, and the implementation into the final model, by the assistance of custom electronic-design-automation flow, is presented. Moreover, we describe the validation procedure of the proposed approach, and the results are compared with the ones obtained by a commercial finite-element-based package used as a benchmark. Two simulation approaches related to specific conversion systems, and related issues, are presented and discussed.

51 citations

Journal ArticleDOI
TL;DR: In this article, the effect of layout parasitics on the internal current distribution of a high-voltage silicon power MOSFET supplied by STMicroelectronics during the turnoff transient is investigated.
Abstract: This paper reports a technique for generating a lumped-element distributed model for silicon power devices that takes into account the effect of layout parasitics. The proposed methodology exploits the high-frequency modeling approach of microstrips and striplines to describe both the passive parts of the device and elementary transistor cells. A semi-empirical model for the elementary transistor cells of the power device is also proposed. Parameter extraction is described and validated by direct comparison with device simulations of an actual device. The proposed modeling approach is employed to investigate the internal current distribution of a high-voltage silicon power MOSFET supplied by STMicroelectronics during the turnoff transient. The tradeoff that must be accomplished between accuracy and complexity is discussed. The effect of increased switching frequency on the device current distribution is also reported explaining how it may lead to performance degradation and device failure.

27 citations

Journal ArticleDOI
TL;DR: In this paper, the authors predict the device lifetime under a power cycling test by a simulation method that is based on a distributed self-heating SPICE model and a correlation between numeric extrapolation and experimental data is done by considering the Repetitive Avalanche test, which evaluates the ruggedness of a power device.
Abstract: The purpose of this paper is to predict the device lifetime under a power cycling test by a simulation method that is based on a distributed self-heating SPICE model. Correlation between numeric extrapolation and experimental data is done by considering the Repetitive Avalanche test, a particular active temperature cycling that evaluates the ruggedness of a power device. The considered failure mechanism is due to front metal aging that produces contact resistance degradation. This phenomenon is strongly dependent on temperature, and by the proposed simulation tool, validated with experimental data, it is possible to evaluate the accurate temperature map and, consequently, predict the lifetime.

18 citations

Patent
11 Jul 2007
TL;DR: In this paper, the authors proposed an electrostatic discharge protection circuit (EDPC) consisting of a first Zener diode having a cathode terminal and an anode terminal.
Abstract: An electro-static discharge protection circuit including: a first input terminal and a second input terminal; a first output terminal coupled to the first input terminal, and a second output terminal coupled to the second input terminal; a first circuit branch connected between the first input terminal and the second input terminal, said first circuit branch including at least one first Zener diode having a cathode terminal and an anode terminal; a second circuit branch connected between the first output terminal and the second output terminal, wherein the first circuit branch comprises a load element coupled between the second input terminal and the anode terminal of the at least one first Zener diode; the second circuit branch includes a first transistor having a control terminal adapted to receive a transistor control voltage, the first transistor being coupled to the load element so as to receive from the load element the transistor control voltage.

17 citations

Journal ArticleDOI
TL;DR: Electro-thermal-mechanical simulation by Finite Element Model (FEM) has been employed in fatigue analysis of a MOSFET structure under electro-Thermal stress and it has been observed that thermal cycling to the point of maximum stress in the solder layer occurs at the edge of the die.

13 citations


Cited by
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Patent
13 Oct 2009
TL;DR: In this article, a portable electronic device includes a touch-sensitive display and a piezoelectric actuator disposed and preloaded on a support and arranged to provide tactile feedback to the touch sensitive display in response to an actuation signal.
Abstract: A portable electronic device includes a touch-sensitive display and a piezoelectric actuator disposed and preloaded on a support and arranged to provide tactile feedback to the touch-sensitive display in response to an actuation signal. The touch-sensitive display may be biased toward the piezoelectric actuator to preload the piezoelectric actuator.

180 citations

Journal ArticleDOI
TL;DR: A quick and efficient evaluation judgment for the thermal management of the IGBTs depended on the requirements on the junction-to-case thermal resistance and equivalent heat transfer coefficient of the test samples is proposed.
Abstract: As an increasing attention towards sustainable development of energy and environment, the power electronics (PEs) are gaining more and more attraction on various energy systems. The insulated gate bipolar transistor (IGBT), as one of the PEs with numerous advantages and potentials for development of higher voltage and current ratings, has been used in a board range of applications. However, the continuing miniaturization and rapid increasing power ratings of IGBTs have remarkable high heat flux, which requires complex thermal management. In this paper, studies of the thermal management on IGBTs are generally reviewed including analyzing, comparing, and classifying the results originating from these researches. The thermal models to accurately calculate the dynamic heat dissipation are divided into analytical models, numerical models, and thermal network models, respectively. The thermal resistances of current IGBT modules are also studied. According to the current products on a number of IGBTs, we observe that the junction-to-case thermal resistance generally decreases inversely in terms of the total thermal power. In addition, the cooling solutions of IGBTs are reviewed and the performance of the various solutions are studied and compared. At last, we have proposed a quick and efficient evaluation judgment for the thermal management of the IGBTs depended on the requirements on the junction-to-case thermal resistance and equivalent heat transfer coefficient of the test samples.

171 citations

Journal ArticleDOI
TL;DR: In this paper, the authors review recent progress in AlGaN/GaN HEMTs, including the following sections: challenges in device fabrication and optimizations, and some promising device structures from simulation studies.
Abstract: GaN based high electron mobility transistors (HEMTs) have demonstrated extraordinary features in the applications of high power and high frequency devices. In this paper, we review recent progress in AlGaN/GaN HEMTs, including the following sections. First, challenges in device fabrication and optimizations will be discussed. Then, the latest progress in device fabrication technologies will be presented. Finally, some promising device structures from simulation studies will be discussed.

93 citations

Journal ArticleDOI
TL;DR: In this article, the authors developed a C -V characterization system for high-voltage power transistors (e.g., MOSFET, insulated gate bipolar transistor, and JFET), which realizes the selective measurement of a specified capacitance from among several capacitances integrated in one device.
Abstract: The switching behavior of semiconductor devices responds to charge/discharge phenomenon of terminal capacitance in the device. The differential capacitance in a semiconductor device varies with the applied voltage in accordance with the depleted region thickness. This study develops a C - V characterization system for high-voltage power transistors (e.g., MOSFET, insulated gate bipolar transistor, and JFET), which realizes the selective measurement of a specified capacitance from among several capacitances integrated in one device. Three capacitances between terminals are evaluated to specify device characteristics-the capacitance for gate-source, gate-drain, and drain-source. The input, output, and reverse transfer capacitance are also evaluated to assess the switching behavior of the power transistor in the circuit. Thus, this paper discusses the five specifications of a C -V characterization system and its measurement results. Moreover, the developed C -V characterization system enables measurement of the transistor capacitances from its blocking condition to the conducting condition with a varying gate bias voltage. The measured C -V characteristics show intricate changes in the low-bias-voltage region, which reflect the device structure. The monotonic capacitance change in the high-voltage region is attributable to the expansion of the depletion region in the drift region. These results help to understand the dynamic behavior of high-power devices during switching operation.

93 citations

Patent
13 Oct 2009
TL;DR: In this paper, a method for determining an adjustable response setting for an electronic device, detecting a touch event on a touch-sensitive display of the electronic device and imparting, by an actuator, a first force on the touch sensitive display by increasing the first force over a ramp-up time period and reducing the first forces over a depression time period.
Abstract: A method includes determining an adjustable response setting for an electronic device, detecting a touch event on a touch-sensitive display of the electronic device, and imparting, by an actuator, a first force on the touch-sensitive display by increasing the first force over a ramp-up time period and reducing the first force over a depression time period, to simulate actuation of a switch based on the adjustable response setting.

88 citations