Gao Zhiqiang

Bio: Gao Zhiqiang is an academic researcher. The author has contributed to research in topics: Nanoelectronics & CMOS. The author has an hindex of 1, co-authored 1 publications receiving 4 citations.

Silicon Nanowire Field Effect Devices By Top-Down CMOS Technology

Abstract: There has been tremendous advancement in the development of novel nano-technologies for future CMOS nanoelectronics. The challenges and opportunities have been widely discussed with the focus on the choice of materials, processes of implementation and innovative non-classical device architectures to continuously meet the scaling requirements. Among the non-classical device architectures, Gate All Around (GAA) FET with nanowire (NW) channel body offers the ultimate electro-static control and thus has the potential to push the gate length to few nanometers. The key challenge for NWs to be widely adopted in semiconductor industry is that they have to be formed by large scale manufacturing methods. Especially, for CMOS applications, the methods should not lead to contamination issues.

2007 IEEE Device Research Conference: Tour de Force Multigate and Nanowire Metal Oxide Semiconductor Field-Effect Transistors and Their Application.

Abstract: Scaling of the conventional planar complementary metal oxide semiconductor (CMOS) faces many challenges. Top-down fabricated gate-all-around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent these limitations to boost the device scalability and performance. Beyond applications in CMOS technology, the thus fabricated Si nanowire arrays can be explored as biosensors, providing a possible route to multiplexed label-free electronic chips for molecular diagnostics.

Strained Silicon Nanowire Transistors With Germanium Source and Drain Stressors

Abstract: We report the first demonstration of pure germanium (Ge) source/drain (S/D) stressors on the ultranarrow or ultrathin Si S/D regions of nanowire FETs with gate lengths down to 5 nm. Ge S/D compressively strains the channel to provide up to ~ 100% I Dsat enhancement. We also introduce a novel Melt-Enhanced Dopant diffusion and activation technique to form fully embedded Si0.15Ge0.85 S/D stressors in nanowire FETs, further boosting the channel strain and achieving ~ 125% I Dsat enhancement.

Vertical Nanowire Gate-All-Around p-type Tunneling Field-Effect Transistor With Si 0.8 Ge 0.2 /Si Heterojunction

Abstract: We present a CMOS compatible p-type gate-all-around (GAA) vertical silicon nanowire tunneling field effect transistor (TFET) featuring Si0.8Ge0.2 source with silicon channel. Besides heterojunction on source side, the highly abrupt doping profile at source-to-channel junction is achieved by low temperature dopant segregation. The fabricated devices display subthreshold slope (SS) as low as 30mV/dec over one decade of drain current, which remains below 60 mV/dec over 3 decades. In addition, our TFET showed reasonable Ion/Ioff ratio of (10 4 ) and low drain induced barrier lowering (DIBL) of 40 mV/V.

Drain current characteristics of silicon nanowire field effect transistor

Abstract: This paper presents the simulation study of characteristics of an 11nm Silicon Nanowire Field Effect Transistor. This architecture is applicable for ultra-scaled devices up to sub-11 nm technology nodes that employ silicon films of a few nm in thickness. The defining characteristics of ultrathin silicon devices such as Short Channel Effects and Quasi-Ballistic transport are considered in modelling the device. Device geometries play a very important role in short channel devices, and hence their impact on drain current is also analyzed by varying the silicon and oxide thickness. The proposed simulation model gives a detailed outlook on the characteristics of the nanowire device in the inversion regime.