Geert Eneman

Bio: Geert Eneman is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: MOSFET & Leakage (electronics). The author has an hindex of 33, co-authored 234 publications receiving 3886 citations. Previous affiliations of Geert Eneman include Research Foundation - Flanders & IMEC.

Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance

Abstract: 7cm 2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at 6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for p/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H2 anneal for device performance is shown.

Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

Abstract: In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling.

Vertical GAAFETs for the Ultimate CMOS Scaling

Abstract: In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules

High-Performance Deep Submicron Ge pMOSFETs With Halo Implants

Abstract: Ge pMOSFETs with HfO2 gate dielectric and gate lengths down to 125 nm are fabricated in a Si-like process. Long-channel hole mobilities exceed the universal curve for Si by more than 2.5 times for vertical effective fields as large as 1 MV/cm. The mobility enhancement is found to be relevant at submicron gate lengths, and a drive current of 1034 muA/mum is achieved for L=125 nm at VG-VT=VD=-1.5 V. The introduction of halo implants allows significantly improved control of short-channel effects, with approximately three orders of magnitude reduction in source junction off-current. VT rolloff and drain-induced barrier lowering are reduced from 207 mV and 230 mV/V to 36 mV and 54 mV/V, respectively, for the highest n-well dose investigated. Four key logic benchmarking metrics are used to demonstrate that Ge is able to outperform Si down to the shortest investigated gate length, with an almost twofold improvement in intrinsic gate delay. ION=722 muA/mum is demonstrated for IOFF=11 nA/mum at a power supply voltage of -1.5 V, when evaluating from the source.

Fast parallel algorithms for short-range molecular dynamics

Abstract: Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Electronic Transport In Mesoscopic Systems

Abstract: Thank you very much for reading electronic transport in mesoscopic systems. Maybe you have knowledge that, people have look numerous times for their favorite readings like this electronic transport in mesoscopic systems, but end up in harmful downloads. Rather than reading a good book with a cup of tea in the afternoon, instead they juggled with some harmful bugs inside their computer. electronic transport in mesoscopic systems is available in our book collection an online access to it is set as public so you can get it instantly. Our book servers spans in multiple locations, allowing you to get the most less latency time to download any of our books like this one. Merely said, the electronic transport in mesoscopic systems is universally compatible with any devices to read.

Review: Semiconductor Piezoresistance for Microsystems

Abstract: Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.

High-performance CMOS variability in the 65-nm regime and beyond

Abstract: Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed. Process-, device-, and circuit-level responses to systematic and random components of tolerance are considered. Exploratory, novel structures emerging as evolutionary CMOS replacements are likely to change the nature of variability in the coming generations.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results