Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost It is challenging to improve all of these factors simultaneously To advance datacenter capabilities beyond what commodity server designs can provide, we designed and built a composable, reconfigurable hardware fabric based on field programmable gate arrays (FPGA) Each server in the fabric contains one FPGA, and all FPGAs within a 48-server rack are interconnected over a low-latency, high-bandwidth networkWe describe a medium-scale deployment of this fabric on a bed of 1632 servers, and measure its effectiveness in accelerating the ranking component of the Bing web search engine We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power, and resilience of the system Under high load, the large-scale reconfigurable fabric improves the ranking throughput of each server by 95% at a desirable latency distribution or reduces tail latency by 29% at a fixed throughput In other words, the reconfigurable fabric enables the same throughput using only half the number of servers

/pdf/a-reconfigurable-fabric-for-accelerating-large-scale-4075xboyh9.pdf

A reconfigurable fabric for accelerating large-scale datacenter services

Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we have designed and built a composable, reconfigurablefabric to accelerate portions of large-scale software services. Each instantiation of the fabric consists of a 6x8 2-D torus of high-end Stratix V FPGAs embedded into a half-rack of 48 machines. One FPGA is placed into each server, accessible through PCIe, and wired directly to other FPGAs with pairs of 10 Gb SAS cablesIn this paper, we describe a medium-scale deployment of this fabric on a bed of 1,632 servers, and measure its efficacy in accelerating the Bing web search engine. We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power, and resilience of the system when ranking candidate documents. Under high load, the largescale reconfigurable fabric improves the ranking throughput of each server by a factor of 95% for a fixed latency distribution--- or, while maintaining equivalent throughput, reduces the tail latency by 29%

/pdf/a-reconfigurable-fabric-for-accelerating-large-scale-1gqzfuqd5z.pdf

Hyperscale datacenter providers have struggled to balance the growing need for specialized hardware (efficiency) with the economic benefits of homogeneity (manageability) In this paper we propose a new cloud architecture that uses reconfigurable logic to accelerate both network plane functions and applications This Configurable Cloud architecture places a layer of reconfigurable logic (FPGAs) between the network switches and the servers, enabling network flows to be programmably transformed at line rate, enabling acceleration of local applications running on the server, and enabling the FPGAs to communicate directly, at datacenter scale, to harvest remote FPGAs unused by their local servers We deployed this design over a production server bed, and show how it can be used for both service acceleration (Web search ranking) and network acceleration (encryption of data in transit at high-speeds) This architecture is much more scalable than prior work which used secondary rack-scale networks for inter-FPGA communication By coupling to the network plane, direct FPGA-to-FPGA messages can be achieved at comparable latency to previous work, without the secondary network Additionally, the scale of direct inter-FPGA messaging is much larger The average round-trip latencies observed in our measurements among 24, 1000, and 250,000 machines are under 3, 9, and 20 microseconds, respectively The Configurable Cloud architecture has been deployed at hyperscale in Microsoft's production datacenters worldwide

/pdf/a-cloud-scale-acceleration-architecture-8ejpq6fh99.pdf

A cloud-scale acceleration architecture

This paper describes a heterogeneous computer cluster called Axel. Axel contains a collection of nodes; each node can include multiple types of accelerators such as FPGAs (Field Programmable Gate Arrays) and GPUs (Graphics Processing Units). A Map-Reduce framework for the Axel cluster is presented which exploits spatial and temporal locality through different types of processing elements and communication channels. The Axel system enables the first demonstration of FPGAs, GPUs and CPUs running collaboratively for N-body simulation. Performance improvement from 4.4 times to 22.7 times has been achieved using our approach, which shows that the Axel system can combine the benefits of the specialization of FPGA, the parallelism of GPU, and the scalability of computer clusters.

/pdf/axel-a-heterogeneous-cluster-with-fpgas-and-gpus-31xfy7a3nz.pdf

Axel: a heterogeneous cluster with FPGAs and GPUs

We present the initial results from the FHPCA Supercomputer project at the University of Edinburgh. The project has successfully built a general-purpose 64 FPGA computer and ported to it three demonstration applications from the oil, medical and finance sectors. This paper describes in brief the machine itself - Maxwell - its hardware and software environment and presents very early benchmark results from runs of the demonstrators.

/pdf/maxwell-a-64-fpga-supercomputer-3a19lsm5nv.pdf

Maxwell - a 64 FPGA Supercomputer

This paper reviews the current state of the art in highperformance reconfigurable computing (HPRC) from the perspective of EPCC, the high-performance computing centre at the University of Edinburgh. We look at architectural and programming trends and assess some of the challenges that HPRC needs to address in order to drive itself across the chasm from the optimistic early adopters to the pragmatic early majority.

High-Performance Reconfigurable Computing - the View from Edinburgh

We describe the FPGA HPC Alliance's parallel toolkit (PTK), an initial step towards the standardization of high-level configuration and APIs for high-performance reconfigurable computing (HPRC). We discuss the motivation and challenges of reaping the performance benefits of FPGAs for memory-bound HPC codes and describe the approach we have taken on the FHPCA supercomputer Maxwell.

The FPGA High-Performance Computing Alliance Parallel Toolkit

This paper proposes a hybrid communication medium for on-chip communication targeting adaptive SoC architectures. Unlike the work carried out in literature, where the term "hybrid" is used for the existence of more then one topologies for communication, the novelty of the proposed medium lies in combining two different communication media. In this paper, global bus and crossbars co-exist in an SoC. RFID Tag Reader is used as the targeted application and bus based system and crossbars based system implementation has been used for comparison purposes. RTL level implementation of the proposed communication structure is carried out for accurate power and area calculations. Results have demonstrated the effectiveness of hybrid communication medium over traditional bus and crossbars based SoC.

Geoff Cawood

Papers

Maxwell - a 64 FPGA Supercomputer

High-Performance Reconfigurable Computing - the View from Edinburgh

The FPGA High-Performance Computing Alliance Parallel Toolkit

Hybrid Communication Medium for Adaptive SoC Architectures