George D. Gristede

TL;DR: A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers by employing a dataflow architecture and an on-chip scratchpad hierarchy.

TL;DR: In this article, a method of automatically selecting object size in an integrated circuit includes the steps of providing a circuit topology having objects disposed therein, inputting equations associated with the objects to provide sizing adjustment for the objects, assigning parameter values in the equations based on physical constraints of the circuit for one or more objects, selecting one ormore objects to be sized, evaluating cones of influence for the selected to identify influenced objects influenced by a change in the selected object and computing for each selected objects and influenced objects, a size in accordance with the associated equation until a user defined criteria is

TL;DR: A fast, low-power, binary carry-lookahead, 64-bit dynamic parallel adder architecture for high-frequency microprocessors with enhanced testability and easily migratable to multigigahertz microprocessor designs is presented.

TL;DR: Circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology are described and described.

TL;DR: RaPiD, a multi-tera operations per second (TOPS) AI hardware accelerator core that is built from the ground-up using AxC techniques across the stack including algorithms, architecture, programmability, and hardware, is presented.