Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges

Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

In this paper, recent progress of binary metal-oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed.

Metal–Oxide RRAM

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

The authors of the International Technology Roadmap for Semiconductors-the industry consensus set of goals established for advancing silicon integrated circuit technology-have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of 'memristors' or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform 'stateful' logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable.

‘Memristive’ switches enable ‘stateful’ logic operations via material implication

The kinetics of the switching process in Cu–SiO2-based electrochemical metallization memory cells was investigated as a function of the switching voltage and the SiO2 film thickness. We observe an exponential dependence of the switching rate on the switching voltage and no significant thickness dependence in the range from 5to20nm SiO2. We conclude from our data that the cathodic electrodeposition represents the rate-limiting step of the switching kinetics. The voltage-time dilemma seems to be overcome by the exponential dependence of the switching rate in combination with a threshold voltage presumably originating from a nucleation overpotential.

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Electrode kinetics of Cu–SiO2-based resistive switching cells: Overcoming the voltage-time dilemma of electrochemical metallization memories

Electrochemical equilibrium and the transfer of mass and charge through interfaces at the atomic scale are of fundamental importance for the microscopic understanding of elementary physicochemical processes. Approaching atomic dimensions, phase instabilities and instrumentation limits restrict the resolution. Here we show an ultimate lateral, mass and charge resolution during electrochemical Ag phase formation at the surface of RbAg(4)I(5) superionic conductor thin films. We found that a small amount of electron donors in the solid electrolyte enables scanning tunnelling microscope measurements and atomically resolved imaging. We demonstrate that Ag critical nucleus formation is rate limiting. The Gibbs energy of this process takes discrete values and the number of atoms of the critical nucleus remains constant over a large range of applied potentials. Our approach is crucial to elucidate the mechanism of atomic switches and highlights the possibility of extending this method to a variety of other electrochemical systems.

Atomically controlled electrochemical nucleation at superionic solid electrolyte surfaces

The impact of the electrochemical nucleation on the switching kinetics in many nanoscaled redox-based resistive switching memories is critically discussed. In the case of the atomic switch, the system is site invariant and the nucleation process is strictly localized below the STM tip. Using RbAg4I5 solid electrolyte, nucleation was found to be rate limiting. The electrochemical metallization memory cells (gapless type atomic switch) operate at conditions closer to the conventional nucleation. They introduce additional difficulties for interpretation of the experimental results due to formation of hillocks, of surface oxide barrier films, induction of strain, and the influence of the high electric field. In valence change memories, the nucleation seems to be less important because of the higher applied voltages. The results are discussed in the context of the atomistic theory of electrochemical nucleation. We believe that re-analysis of the experimental data for many systems will reveal that the nucleation is limiting the switching time.

Nucleation and growth phenomena in nanosized electrochemical systems for resistive switching memories

Currently, there is great interest in using solid electrolytes to develop resistive switching based nonvolatile memories (RRAM) and logic devices. Despite recent progress, our understanding of the microscopic origin of the switching process and its stochastic behavior is still limited. In order to understand this behavior, we present a statistical “breakdown” analysis performed on Cu doped Ge0.3Se0.7 based memory devices under elevated temperature and constant voltage stress conditions. Following the approach of electrochemical phase formation, the precursor of the “ON resistance switching” is considered to be nucleation — the emergence of small clusters of atoms carrying the basic properties of the new phase which forms the conducting filament. Within the framework of nucleation theory, the observed fluctuations in the time required for “ON resistance switching” are found to be consistent with the stochastic nature of critical nucleus formation.

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Georgi Staikov

Papers

Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges

Electrode kinetics of Cu–SiO2-based resistive switching cells: Overcoming the voltage-time dilemma of electrochemical metallization memories

Atomically controlled electrochemical nucleation at superionic solid electrolyte surfaces

Nucleation and growth phenomena in nanosized electrochemical systems for resistive switching memories

On the stochastic nature of resistive switching in Cu doped Ge0.3Se0.7 based memory devices