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Author

Gerd Ascheid

Bio: Gerd Ascheid is an academic researcher from RWTH Aachen University. The author has contributed to research in topics: MIMO & MPSoC. The author has an hindex of 32, co-authored 464 publications receiving 4957 citations. Previous affiliations of Gerd Ascheid include Eindhoven University of Technology & Synopsys.


Papers
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Proceedings ArticleDOI
08 Jun 2008
TL;DR: An integrated framework, MAPS, which aims at parallelizing C applications for MPSoC platforms and extracts coarse-grained parallelism on a novel granularity level is proposed.
Abstract: In the past few years, MPSoC has become the most popular solution for embedded computing. However, the challenge of programming MPSoCs also comes as the biggest side-effect of the solution. Especially, when designers have to face the legacy C code accumulated through the years, the tool support is mostly unsatisfactory. In this paper, we propose an integrated framework, MAPS, which aims at parallelizing C applications for MPSoC platforms. It extracts coarse-grained parallelism on a novel granularity level. A set of tools have been developed for the framework. We will introduce the major components and their functionalities. Two case studies will be given, which demonstrate the use of MAPS on two different kinds of applications. In both cases the proposed framework helps the programmer to extract parallelism efficiently.

128 citations

Proceedings ArticleDOI
10 Jun 2014
TL;DR: The lower bound on the average post-processing uplink signal to interference-plus-noise ratio (SINR) is derived with individual power assignment between pilot and data transmissions for each user, which facilitates a joint iterative uplink pilot andData power control strategy that minimizes the sum transmit power of all users subject to the per-user SINR and per- user power constraints.
Abstract: In the current literature considering multi-cell multi-user massive multiple-input multiple-output (MU-Massive-MIMO) systems, equal uplink power allocation among users is typically assumed, which does not exploit the potential of peruser power control. By contrast, in this paper we apply multi-cell uplink power control, assuming the minimum mean-square-error receiver based on the pilot contaminated channel estimation and a very large but finite number of antennas at the base station. We derive the lower bound on the average post-processing uplink signal to interference-plus-noise ratio (SINR) with individual power assignment between pilot and data transmissions for each user, which facilitates a joint iterative uplink pilot and data power control strategy that minimizes the sum transmit power of all users subject to the per-user SINR and per-user power constraints. The convergence of the proposed algorithm to a unique fixed point optimal solution is discussed for both single- and multi-user scenarios. Numerical results indicate the significance of uplink power control which further improves the energy efficiency in MU-Massive-MIMO systems.

105 citations

Journal ArticleDOI
TL;DR: A framework is presented that provides support for mapping multiple dataflow applications onto heterogeneous MPSoCs, is aware of design constraints, provides different means for performance estimation and supports a variety of mapping heuristics.
Abstract: Processor Systems on Chip (MPSoCs) in order to cope with the increasing applications demands and the tight energy budget of portable devices. The complexity of these systems makes them difficult to program, which has caused academia and industry to look for alternative methodologies and models. In the particular case of multimedia and baseband processing, dataflow models are being proposed and appear to be a sensible choice to represent applications. While high-level models, like dataflow, increase programmers' productivity, new, powerful tools are badly required that lower the abstract specification into an efficient implementation. In this paper, a framework is presented that provides support for mapping multiple dataflow applications onto heterogeneous MPSoCs. The framework is aware of design constraints, provides different means for performance estimation and supports a variety of mapping heuristics. The tool is showcased on three applications on a virtual platform containing heterogeneous processing elements. The heuristics for single applications reported a speedup of up to 40% when compared against random walk. The multi-application component helped to find an appropriate scheduling configuration that met real-time constraints when the three applications were running simultaneously.

102 citations

Proceedings ArticleDOI
07 Mar 2005
TL;DR: A SystemC-based simulation framework, which enables the quantitative evaluation of application-to-platform mappings by means of an executable performance model, and highlights the potential for optimization of an efficient design space exploration environment.
Abstract: Heterogeneous Multi-Processor SoC platforms bear the potential to optimize conflicting performance, flexibility and energy efficiency constraints as imposed by demanding signal processing and networking applications. However, in order to take advantage of the available processing and communication resources, an optimal mapping of the application tasks onto the platform resources is of crucial importance. In this paper, we propose a SystemC-based simulation framework, which enables the quantitative evaluation of application-to-platform mappings by means of an executable performance model. Key element of our approach is a configurable event-driven Virtual Processing Unit to capture the timing behavior of multi-processor/multi-threaded MP-SoC platforms. The framework features an XML-based declarative construction mechanism of the performance model to significantly accelerate the navigation in large design spaces. The capabilities of the proposed framework in terms of design space exploration is presented by a case study of a commercially available MP-SoC platform for networking applications. Focussing on the application to architecture mapping, our introduced framework highlights the potential for optimization of an efficient design space exploration environment.

102 citations

Proceedings ArticleDOI
06 Mar 2006
TL;DR: This paper proposes a framework that enables software development, verification and evaluation from the very beginning of MP-SoC design cycle, and allows a co-development of the hardware and the software components in a tightly coupled loop where the hardware can be refined by considering the requirements of the software in a stepwise manner.
Abstract: The increasing demands of high-performance in embedded applications under shortening time-to-market has prompted system architects in recent time to opt for multi-processor systems-on-chip (MP-SoCs) employing several programmable devices. The programmable cores provide a high amount of flexibility and reusability, and can be optimized to the requirements of the application to deliver high-performance as well. Since application software forms the basis of such designs, the need to tune the underlying SoC architecture for extracting maximum performance from the software code has become imperative. In this paper, we propose a framework that enables software development, verification and evaluation from the very beginning of MP-SoC design cycle. Unlike traditional SoC design flows where software design starts only after the initial SoC architecture is ready, our framework allows a co-development of the hardware and the software components in a tightly coupled loop where the hardware can be refined by considering the requirements of the software in a stepwise manner. The key element of this framework is the integration of a fine-grained software instrumentation tool into a system-level-design (SLD) environment to obtain accurate software performance and memory access statistics. The accuracy of such statistics is comparable to that obtained through instruction set simulation (ISS), while the execution speed of the instrumented software is almost an order of magnitude faster than ISS. Such a combined design approach assists system architects to optimize both the hardware and the software through fast exploration cycles, and can result in far shorter design cycles and high productivity. We demonstrate the generality and the efficiency of our methodology with two case studies selected from two most prominent and computationally intensive embedded application domains.

96 citations


Cited by
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Journal ArticleDOI

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08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

01 Jan 2016
TL;DR: The table of integrals series and products is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can get it instantly.
Abstract: Thank you very much for downloading table of integrals series and products. Maybe you have knowledge that, people have look hundreds times for their chosen books like this table of integrals series and products, but end up in harmful downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they cope with some harmful virus inside their laptop. table of integrals series and products is available in our book collection an online access to it is set as public so you can get it instantly. Our book servers saves in multiple locations, allowing you to get the most less latency time to download any of our books like this one. Merely said, the table of integrals series and products is universally compatible with any devices to read.

4,085 citations

Journal ArticleDOI
TL;DR: An overview of progress in the area of multiple input multiple output (MIMO) space-time coded wireless systems is presented and the state of the art in channel modeling and measurements is presented, leading to a better understanding of actual MIMO gains.
Abstract: This paper presents an overview of progress in the area of multiple input multiple output (MIMO) space-time coded wireless systems. After some background on the research leading to the discovery of the enormous potential of MIMO wireless links, we highlight the different classes of techniques and algorithms proposed which attempt to realize the various benefits of MIMO including spatial multiplexing and space-time coding schemes. These algorithms are often derived and analyzed under ideal independent fading conditions. We present the state of the art in channel modeling and measurements, leading to a better understanding of actual MIMO gains. Finally, the paper addresses current questions regarding the integration of MIMO links in practical wireless systems and standards.

2,488 citations

Journal ArticleDOI

2,415 citations

01 Apr 1997
TL;DR: The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity.
Abstract: The objective of this paper is to give a comprehensive introduction to applied cryptography with an engineer or computer scientist in mind. The emphasis is on the knowledge needed to create practical systems which supports integrity, confidentiality, or authenticity. Topics covered includes an introduction to the concepts in cryptography, attacks against cryptographic systems, key use and handling, random bit generation, encryption modes, and message authentication codes. Recommendations on algorithms and further reading is given in the end of the paper. This paper should make the reader able to build, understand and evaluate system descriptions and designs based on the cryptographic components described in the paper.

2,188 citations