Gheorghe Stefan

Bio: Gheorghe Stefan is an academic researcher from Politehnica University of Bucharest. The author has contributed to research in topics: Content-addressable memory & Clock signal. The author has an hindex of 9, co-authored 58 publications receiving 293 citations. Previous affiliations of Gheorghe Stefan include University of Bucharest & Saint Anselm College.

A memory engine for the inspection and manipulation of data

Abstract: A memory engine combines associative memory and random-access memory for enabling fast string search, insertion, and deletion operations to be performed on data and includes a memory device for temporarily storing the data as a string of data characters. A controller is utilized for selectively outputting one of a plurality of commands to the memory device and receives data feedback therefrom, the memory device inspects data characters in the string in accordance with the commands outputted by the controller. A clock device is also utilized for outputting a clock signal comprised of a predetermined number of clock cycles per second to the memory device and the controller, the memory device inspecting and selectively manipulating one of the data characters within one of the clock cycles.

Integrated processor array, instruction sequencer and I/O controller

Abstract: A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation. The I/O controller controls the transfer of I/O data to and from the processing engines in parallel with the processing controlled by the instruction sequencer. The processing engines themselves are constructed with an integer arithmetic and logic unit (ALU), a 1-bit ALU, a decision unit, and registers. Instructions from the instruction sequencer direct the integer ALU to perform integer operations according to logic states stored in the 1-bit ALU and data stored in the decision unit. The 1-bit ALU and the decision unit can modify their stored information in the same clock cycle as the integer ALU carries out its operation. The processing engines also contain a local memory for storing instructions and data.

Not multi-, but many-core: designing integral parallel architectures for embedded computation

Abstract: Recent embedded systems have switched to fully programmable parallel architectures. To make sure all corner cases usually present in real applications are supported and efficiently implemented in this switch of implementation, new solutions must be found. We introduce the integral parallel architecture (IPA) as a solution supporting intensive data computation in System-on-a-chip (Soc) implementations, fitting in a small area, and requiring low power. An IPA supports naturally all three possible styles of parallelism: data, time, and speculative.As an illustrative example, we present the BA1024 chip, a fully programmable SoC designed by BrightScale, Inc. for HDTV codecs. Its main performance figures include 60 GOPS/Watt and 2 GOPS/mm2, representing an efficient IPA approach for embedded computation.

The CA1024: A fully programmable system-on-chip for costeffective HDTV media processing

Abstract: This article consists of a collection of slides from the author's conference presentation onConnex's CA1024, a fully programmable system-on-chip HDTV media processing system. Some of the specific topics discussed include: the special features and specifications of CA1024; deployment and applications for it use; media processing capabilities; and performance evaluation for system processing.

Parallel data processing apparatus

Abstract: A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial instruction stream, and a distribution unit operable to distribute the serial instruction stream to an array of processing elements.

A literature survey

Abstract: This report sums up a literature survey of meta-analytical methods. The objective of the survey is to cover the state-of-the-art in three areas of meta-analysis where we believe there are still unsolved problems and where the choice of approach may still be contentious. These areas are the treatment of heterogeneity, the problem of publication bias and the assessment and incorporation of the quality of the individual studies.