Spintronics, or spin electronics, involves the study of active control and manipulation of spin degrees of freedom in solid-state systems. This article reviews the current status of this subject, including both recent advances and well-established results. The primary focus is on the basic physical principles underlying the generation of carrier spin polarization, spin dynamics, and spin-polarized transport in semiconductors and metals. Spin transport differs from charge transport in that spin is a nonconserved quantity in solids due to spin-orbit and hyperfine coupling. The authors discuss in detail spin decoherence mechanisms in metals and semiconductors. Various theories of spin injection and spin-polarized transport are applied to hybrid structures relevant to spin-based devices and fundamental studies of materials properties. Experimental work is reviewed with the emphasis on projected applications, in which external electric and magnetic fields and illumination by light will be used to control spin and charge dynamics to create new functionalities not feasible or ineffective with conventional electronics.

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Spintronics: Fundamentals and applications

1. Introduction and overview 2. Film stress and substrate curvature 3. Stress in anisotropic and patterned films 4. Delamination and fracture 5. Film buckling, bulging and peeling 6. Dislocation formation in epitaxial systems 7. Dislocation interactions and strain relaxation 8. Equilibrium and stability of surfaces 9. The role of stress in mass transport.

Thin Film Materials: Stress, Defect Formation and Surface Evolution

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

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Device scaling limits of Si MOSFETs and their application dependencies

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.

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Rationale and challenges for optical interconnects to electronic chips

This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

We have fabricated strained Ge channel p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) on Si0.3Ge0.7 virtual substrates. The poor interface between silicon dioxide (SiO2) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400 °C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly eight times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm2/V s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement-mode MOSFET with buried channel-like transport characteristics.

Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si/sub 1-x/Ge/sub x/-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si/sub 0.75/Ge/sub 0.26/ and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si/sub 1-x/Ge/sub x/ layer.

Electron mobility enhancement in strained-Si n-MOSFETs fabricated on SiGe-on-insulator (SGOI) substrates

Lattice-mismatched relaxed graded composition layers in the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems have recently been created with unprecedented high quality due to advances in understanding the impact of epitaxial growth conditions. The key process–property correlation is the impact of growth conditions on dislocation dynamics. In particular, the SiGe/Si system has recently been well explored experimentally, allowing the dislocation dynamic model to be tested. We show that the dislocation dynamics model is in general applicable to graded layers in any material system as long as dislocation flow is not impeded. In the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems, with moderately dislocated graded layers, these mechanisms can be absent under appropriate growth conditions. However, in all systems, threading dislocation impediments eventually occur under continued deformation through continued grading. The mechanism in SiGe/Si is related to the impediment of dislocation flow from the surface morphology and strain-fields from misfit dislocations. In the III–V systems, we observe that a planar defect, referred to here as branch defects, can form under a wide range of growth conditions, and these defects will lead to inhibited dislocation flow. The quantitative nature of these effects can be empirically modeled with the same dislocation dynamic model by incorporating a composition-dependent change in the effective strain experienced by threading dislocations during grading-induced deformation.

Dislocation dynamics in relaxed graded composition semiconductors

Techniques for fabricating strained Si, SiGe, and Ge on-insulator include SIMOX, Ge condensation and wafer bonding. In this paper, a brief introduction of each method is presented, with a detailed discussion of wafer bonding approaches for strained Si, SiGe, and Ge on-insulator. Wafer bonding with stop layers is found to be the most general approach with the ability to create ultra-thin layers of strained Si, SiGe, and Ge on-insulator with low threading dislocation densities and precise control over layer thickness.

Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques

Recent advances in the understanding and control of threading dislocations in substantially relaxed SiGe buffer layers on Si are presented. A model for threading dislocation flow in relaxed graded SiGe buffers is used to determine the potential lower limit of threading dislocation density in relaxed SiGe buffers. Greater densities than expected from the model are seen in relaxed graded alloys with final concentrations greater than 50%. We show that the culprits of the higher threading dislocation density are threading dislocation pile-ups. Observation of early development of pile-ups confirms that inhomogeneous misfit dislocation densities in the graded buffer form regions of more severe crosshatch on the surface that impede dislocation flow. By using chemomechanical planarization (CMP), deleterious pile-up formation can be avoided, and previously formed pile-ups can be destroyed by regrowth of a graded layer. Experiments with CMP and regrowth of graded layers suggest that dislocation annihilation can be effective at reducing threading dislocation densities to densities of the order expected by the model. High quality Ge on Si layers created with the CMP process were used as templates to grow high quality GaAs on Si with strong room temperature photoluminescence and record minority carrier lifetime.

Gianni Taraschi

Papers

Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates

Electron mobility enhancement in strained-Si n-MOSFETs fabricated on SiGe-on-insulator (SGOI) substrates

Dislocation dynamics in relaxed graded composition semiconductors

Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques

Dislocations in Relaxed SiGe/Si Heterostructures