Gilbert Hendry

Bio: Gilbert Hendry is an academic researcher from Sandia National Laboratories. The author has contributed to research in topics: Photonics & Network on a chip. The author has an hindex of 15, co-authored 33 publications receiving 958 citations. Previous affiliations of Gilbert Hendry include Columbia University & University of Central Florida.

PhoenixSim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks

Abstract: Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power efficient communications both on- and off-chip. Since optical devices are fundamentally different from conventional electronic interconnect technologies, new design methodologies and tools are required to exploit the potential performance benefits in a manner that accurately incorporates the physically different behavior of photonics. We introduce PhoenixSim, a simulation environment for modeling computer systems that incorporates silicon nanophotonic devices as interconnection building blocks. PhoenixSim has been developed as a cross-discipline platform for studying photonic interconnects at both the physical-layer level and at the architectural and system levels. The broad scope at which modeled systems can be analyzed with PhoenixSim provides users with detailed information into the physical feasibility of the implementation, as well as the network and system performance. Here, we describe details about the implementation and methodology of the simulator, and present two case studies of silicon nanophotonic-based networks-on-chip.

Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors

Abstract: Integrated photonics has been slated as a revolutionary technology with the potential to mitigate the many challenges associated with on- and off-chip electrical interconnection networks. To date, all proposed chip-scale photonic interconnects have been based on the crystalline silicon platform for CMOS-compatible fabrication. However, maintaining CMOS compatibility does not preclude the use of other CMOS-compatible silicon materials such as silicon nitride and polycrystalline silicon. In this work, we investigate utilizing devices based on these deposited materials to design photonic networks with multiple layers of photonic devices. We apply rigorous device optimization and insertion loss analysis on various network architectures, demonstrating that multilayer photonic networks can exhibit dramatically lower total insertion loss, enabling unprecedented bandwidth scalability. We show that significant improvements in waveguide propagation and waveguide crossing insertion losses resulting from using these materials enables the realization of topologies that were previously not feasible using only the single-layer crystalline silicon approaches.

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

Abstract: Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely high-bandwidth density and energy-efficient links for on-chip and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this paper, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment. We present a case study of two different photonic networks-on-chip to demonstrate how our improved understanding and modeling of the physical-layer details of photonic communications can be used to better understand the system-level performance impact.

Architectural design exploration of chip-scale photonic interconnection networks using physical-layer analysis

Abstract: Chip-scale photonic interconnection networks have emerged as a promising technology solution that can address many of the scalability challenges facing the communication networks in next-generation high-performance multicore processors. Photonic interconnects can offer significantly higher bandwidth density, lower latencies, and better energy efficiency. Even though photonics exhibits these inherent advantages over electronics, the network designs that can successfully leverage these benefits cannot be straightforwardly extracted from typical electronic network methodologies and must consider the many unique physical-layer constraints of optical technologies. We conduct an architectural exploration of four chip-scale photonic interconnection networks in a novel simulation environment, measuring insertion loss, crosstalk, and power. We also explain and demonstrate the impact of these physical-layer metrics on the scalability, performance, and realizability of each design.

Photonic Network-on-Chip Design

Abstract: Introduction.- Photonic Interconnects.- Silicon Photonics.- Photonic Simulation and Design Space.- Photonic Network Architectures I: Circuit Switching.- Photonic Network Architectures II: Wavelength Arbitration and Routing.- Photonic Network Architectures III: Advanced Photonic Architectures.- Conclusions.

Fast parallel algorithms for short-range molecular dynamics

Abstract: Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Integrated optics

Abstract: In order to enable optical systems to operate with a high degree of compactness and reliability it is necessary to combine large number of optical functions in small monolithic structures. A development, somewhat reminiscent of that that took place in Integrated Electronics, is now beginning to take place in optics. The initial challenge in this emerging field, known appropriately as "Integrated Optics", is to demonstrate the possibility of performing basic optical functions such as light generation, coupling, modulation, and guiding in Integrated Optical configurations. The talk will review the main theoretical and experimental developments to date in Integrated Optics. Specific topics to be discussed include: Material considerations, guiding mechanisms, modulation, coupling and mode losses. The fabrication and applications of periodic thin film structures will be discussed.

WDM-compatible mode-division multiplexing on a silicon chip

Abstract: Significant effort in optical-fibre research has been put in recent years into realizing mode-division multiplexing (MDM) in conjunction with wavelength-division multiplexing (WDM) to enable further scaling of the communication bandwidth per fibre. In contrast, almost all integrated photonics operate exclusively in the single-mode regime. MDM is rarely considered for integrated photonics because of the difficulty in coupling selectively to high-order modes, which usually results in high inter-modal crosstalk. Here we show the first microring-based demonstration of on-chip WDM-compatible mode-division multiplexing with low modal crosstalk and loss. Our approach can potentially increase the aggregate data rate by many times for on-chip ultrahigh bandwidth communications.

DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling

Abstract: With the rise of many-core chips that require substantial bandwidth from the network on chip (NoC), integrated photonic links have been investigated as a promising alternative to traditional electrical interconnects While numerous opto-electronic NoCs have been proposed, evaluations of photonic architectures have thus-far had to use a number of simplifications, reflecting the need for a modeling tool that accurately captures the tradeoffs for the emerging technology and its impacts on the overall network In this paper, we present DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks We explain our modeling framework and perform an energy-driven case study, focusing on electrical technology scaling, photonic parameters, and thermal tuning Our results show the implications of different technology scenarios and, in particular, the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature

System, method, and computer program product for improving memory systems

Abstract: A system, method, and computer program product are provided for a memory system. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit.