Gillis Winderickx

Bio: Gillis Winderickx is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Dielectric & Leakage (electronics). The author has an hindex of 12, co-authored 19 publications receiving 807 citations.

Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance

Abstract: 7cm 2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at 6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for p/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H2 anneal for device performance is shown.

High performance Ge pMOS devices using a Si-compatible process flow

Abstract: Ge pMOS mobilities up to 358 cm2/Vs are demonstrated using a Si-compatible process flow without the incorporation of strain. EOT is approximately 12 Aring with a gate leakage less than 0.01 A/cm 2 at Vt+ 0.6 V. Ge transistors are characterized with gate lengths ranging from 10 mum down to 0.125 mum, the shortest ever reported. We also present the best Ge pMOS drain current to date of 790 muA/mum at Vgt = Vd = -1.5V for an Lg of 0.19 mum

Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

Abstract: We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.

Heavy ion implantation in Ge: Dramatic radiation induced morphology in Ge

Abstract: High dose ion implantation of heavy elements in Ge induces a rough surface and profile distortions when measured with secondary ion mass spectrometry. In the case of Sb large subsurface holes are also induced by the implantation. The formation of these subsurface structures starts abruptly at a dose between 5∙1014 and 1015at∕cm2. The addition of a SiO2 capping layer on top of Ge prevents the formation of the surface roughness, but has limited impact on the void formation. These voids originate from vacancy clustering during the implant process. Anneal studies show that it is impossible to remove these structures by annealing, limiting the usefulness of high dose Sb implants in Ge for junction formation. In the case of As implantation a similar surface roughness is seen but no void formation. Adding a cap layer removes the surface roughness in this case and improves the secondary ion mass spectroscopy profiles.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Academic and industry research progress in germanium nanodevices

Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

Abstract: ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance

Abstract: 7cm 2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at 6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for p/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H2 anneal for device performance is shown.