김태환

Bio: 김태환 is an academic researcher. The author has contributed to research in topics: Physical design. The author has an hindex of 1, co-authored 1 publications receiving 2 citations.

Power and Obstacle Aware 3D Clock Tree Synthesis

Abstract: Clock Network Design (CDN) is a critical step while designing any Integrated-Circuits (ICs). It holds vital importance in the performance of entire circuit. Due to continuous scaling, 3D ICs stacked with TSV are gaining importance, with an objective to continue with the Moore's law. Through-SiliconVia (TSV) provides the vertical interconnection between two die, which allows the electrical signal to flow through it. 3D ICs has many advantages over conventional 2D planar ICs like reduced power, area, cost, wire-length etc. The proposed work is mainly focused on power reduction and obstacle avoidance for 3D ICs. Various techniques have already been introduced for minimizing clock power within specified clock constraints of the 3D CND network. Proposed 3D Clock Tree Synthesis (CTS) is a combination of various algorithms with an objective to meet reduction in power as well as avoidance of obstacle or blockages while routing the clock signal from one sink to other sink. These blockages like RAM, ROM, PLL etc. are fixed during the placement process. The work is carried out mainly in three stepsfirst is Generation of 3D Clock tree avoiding the blockages, then Buffering and Embedding and finally validating the results by SPICE simulation. The experimental result shows that our CTS approach results in significant 9% reduction in power as compare to the existing work.

A clustering technique for fast electrothermal analysis of on-chip power distribution networks

Abstract: This paper presents an equivalent self-consistent electrothermal circuit model for power integrity analysis of large on-chip power distribution networks. Two coupled circuits are used to co-simulate the electrical and thermal behavior of the power grid. After a steady-state analysis, the order of the circuit is strongly reduced by means of a node clustering technique. The obtained low-order circuit allows a cost-effective complete power integrity analysis, including dynamic analysis and evaluation of time-domain features like voltage droop. As a case-study, a 45-nm chip power grid is analyzed: the full circuit for the electrothermal model with 4 million nodes is reduced by a factor of about 3500×, with a relative error on the solution below few percent.

Information-Theoretic Perspective to Thermal Covert Channels

Abstract: Covert communication channels are a significant security threat where the host computer's security policy is bypassed to establish a communication link that can leak sensitive data. Establishing thermal covert channels is feasible because modern processors have accessible temperature sensors that are typically used for dynamic thermal management. In this paper, we first provide an information-theoretic discussion on thermal cover channels and important characteristics such as channel capacity and data modulation methods. Next, we summarize existing thermal covert channel detection methods, including their limitations. We then propose a novel runtime detection method for thermal covert channels where the secret data is encoded via low power programs. Our results demonstrate that the proposed technique can achieve 100% detection accuracy with 0% false positive rate.