A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 μs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.

https://researchrepository.ucd.ie/bitstream/10197/8627/1/2014-05_jssc_w-wu_mm-wave_tx_adpll.pdf

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

In this paper, we propose a method to reduce a flicker (1/f) noise upconversion in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest impedance path. The asymmetric oscillation waveform results in an effective impulse sensitivity function of a nonzero dc value, which facilitates the 1/f noise upconversion into the oscillator’s 1/f3 phase noise. We demonstrate that if the $\omega _{0}$ tank exhibits an auxiliary resonance at 2 $\omega _{0}$ , thereby forcing this current harmonic to flow into the equivalent resistance of the 2 $\omega _{0}$ resonance, then the oscillation waveform would be symmetric and the flicker noise upconversion would be largely suppressed. The auxiliary resonance is realized at no extra silicon area in both inductor- and transformer-based tanks by exploiting different behaviors of inductors and transformers in differential- and common-mode excitations. These tanks are ultimately employed in designing modified class-D and class-F oscillators in 40 nm CMOS technology. They exhibit an average flicker noise corner of less than 100 kHz.

/pdf/a-1-f-noise-upconversion-reduction-technique-for-voltage-xargflo928.pdf

A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators

A digital fractional-N PLL that employs a high resolution TDC and a truly $\Delta \Sigma$ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out $\Delta \Sigma$ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than ${-}$ 106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fs $ _{{\rm rms}}$ integrated jitter. This translates to a FoM $ _{{\rm J}}$ of ${-}$ 240.5 dB, which is the best among the reported fractional-N PLLs.

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Ultra-low-power (ULP) transceivers enable short-range networks of autonomous sensor nodes for wireless personal-area-network (WPAN) applications. RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ULP WPAN radios. Compared to analog PLLs [1], all-digital PLLs (ADPLLs) are preferred in nanoscale CMOS as they offer benefits of smaller area, programmability, capability of extensive self-calibrations, and easy portability [2]. However, analog PLLs dominate the field of ULP WPAN radios [1], since the time-to-digital-converter (TDC) of an ADPLL has traditionally been power hungry. We present a 2.1-to-2.7GHz 860μW fractional-N ADPLL in 40nm CMOS for WPAN applications, which breaks the 1mW barrier and consumes at least 5× lower power compared to state-of-the-art ADPLLs.

9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications

Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications. However, the main obstacle to their full acceptance in the wireless-systems arena is their higher content of output spurious tones, whose level is ultimately set by the nonlinearity of the time-to-digital converter (TDC). The known methods to improve the linearity of the TDC either increase its dissipation and phase noise or require slow foreground calibrations. By contrast, the class of digital PLLs based on a one-bit TDC driven by a multibit digital-to-time converter (DTC) substantially reduces power dissipation and eliminates the TDC nonlinearity issues. Although its spur performance depends on DTC linearity, the modified architecture enables the application of a background adaptive pre-distortion which does not compromise the PLL phase-noise level and power consumption and is much faster than other calibration techniques. This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from -39 to -52 dBc when the pre-distortion is enabled, in-band phase noise of -103 dBc/Hz and power consumption of 4.2 mW.

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-time converter, placed in the feedback path, cancels out the quantization noise introduced by the dithering of the frequency divider modulus and permits to achieve low noise at low power. The PLL is implemented in a standard 65-nm CMOS process. It achieves - 102-dBc/Hz phase noise at 50-kHz offset and a total absolute jitter below 560 fsrms (integrated from 3 kHz to 30 MHz), even in the worst-case of a -42-dBc in-band fractional spur. The synthesizer tuning range spans from 2.92 GHz to 4.05 GHz with 70-Hz resolution. The total power consumption is 4.5 mW, which leads to the best jitter-power trade-off obtained with a fractional-N synthesizer. The synthesizer demonstrates the capability of frequency modulation up to 1.25-Mb/s data rate.

A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- ${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power

Polar or outphasing radio transmitter architectures promise higher efficiency than their Cartesian counterparts [1], but require the adoption of phase modulators with bandwidth about one order of magnitude wider than the channel bandwidth. In contrast to phase-switching approaches [2], efficient implementations of wideband phase modulators are based on the direct frequency modulation (FM) of a PLL and on the two-point signal-injection scheme [3]. Unfortunately, meeting the noise/bandwidth requirements of 4G wireless standards (such as WiMAX) demands fine frequency resolution, tight VCO linearity and accurate synchronization between the two signals injected into the PLL. This paper introduces a digital-intensive phase modulator circuit, which is able to enforce an arbitrary carrier phase change (up to ±π radians) in one clock sample. For a clock frequency of 40MHz, the modulation error, expressed in terms of error vector magnitude (EVM), is below −36dB for a 20Mb/s QPSK-modulated or a 10Mb/s GMSK-modulated carrier at 3.6GHz.

A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With −36 dB EVM at 5 mW Power

Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm $^{2}$ , and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of $-$ 232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of $-$ 243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from $-$ 32 to $-$ 55 dBc.

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

The introduction of inductorless frequency synthesizers into standardized wireless systems still requires a high level of innovation in order to achieve the stringent requirements of low noise and low power consumption. Synthesizers based on the so-called multiplying delay-locked loop (MDLL) represent one of the most promising architectures in this direction [1-3]. An MDLL resembles a ring oscillator, in which the signal edge traveling along the delay line is periodically refreshed by a clean edge of the reference clock. In this manner, the phase noise of the ring oscillator is filtered up to half the reference frequency and the total output jitter is reduced significantly. Unfortunately, the concept of MDLL, and in general of injection locking (IL), is inherently limited to integer-N synthesis, which makes it unacceptable in practical RF systems. A first extension of injection locking to coarse fractional-N resolution has been shown in [4], in which however the fractional resolution is bounded to the inverse of the number of ring-oscillator delay stages. This paper introduces a fractional-N MDLL-based frequency synthesizer with a 1b time/digital converter (TDC), which is able to outreach the performance of inductorless fractional-N synthesizers. The prototype synthesizes frequencies between 1.6 and 1.9GHz with 190Hz resolution and achieves RMS integrated jitter of 1.4ps at 3mW power consumption, even in the worst-case of near-integer channel.

Giovanni Marzin

Papers

A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- ${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With −36 dB EVM at 5 mW Power

A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC