We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mVp-p output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm 2 and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm 2 .

Area-efficient linear regulator with ultra-fast load regulation

The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.

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A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

This paper proposes a transient response enhancement method for low-dropout (LDO) regulator without off-chip capacitors. It’s based on a slew rate enhancement circuit that includes a tail current detection circuit and a pass transistor gate drive circuit. The voltage of the gate of the regulating tube is driven by detecting the change of the output voltage. This paper uses a 0.18 μm MOS process and shows that when the load current changes from 0 to 100 mA within 1 μs, the LDO proposed in this paper can reach a stable voltage within 1.6 μs. Its output voltage overshoot is 1.47 V and undershoot is 0.83 V. 

A Fast Transient Response Capacitorless LDO with Slew Rate Enhancement Design

The present invention relates to a linear regulator with real-time frequency compensation function, which belongs to the technical field of analog integrated circuits. The part of frequency compensation of the present invention includes the dual-frequency compensation networks and compensation transfer switcher, and the pulse delay circuit. The dual-frequency compensation networks and compensation transfer switcher provide the corresponding frequency compensation for linear regulator under two different capacitive loads. The pulse delay circuit generates a set of signals which have a delay related to the switch-pulse signals to control the access of the compensation transfer switcher and capacitive load. The advantages of the present invention are that the circuit structure is simple, without complex feedback control circuits, the excessive power dissipation is extremely low, and it is applied to such special use of linear regulator with switched capacitive load that it can option the loop frequency compensation in real-time to ensure the linear regulator has the optimal stability and load transient response.

Linear regulator with real-time frequency compensation function

This paper proposes a transient response enhancement method for low-dropout (LDO) regulator without off-chip capacitors. It’s based on a slew rate enhancement circuit that includes a tail current detection circuit and a pass transistor gate drive circuit. The voltage of the gate of the regulating tube is driven by detecting the change of the output voltage. This paper uses a 0.18 μm MOS process and shows that when the load current changes from 0 to 100 mA within 1 μs, the LDO proposed in this paper can reach a stable voltage within 1.6 μs. Its output voltage overshoot is 1.47 V and undershoot is 0.83 V.

A new technique for low dropout (LDO) regulators operating without an off-chip capacitor is proposed. The technique restricts the output voltage drop to around 100mV when the load current switches from 0 to 200mA in 50ns. An on-chip load capacitance of 200pF is assumed. The proposed extra circuitry requires only 5 transistors and a small 1pf capacitor, consumes 110μA of quiescent current, and affects the LDO loop operation only when the output changes suddenly. Results are verified in Spice, for a 1.8-V LDO with a 2-V nominal input voltage and a 1.24-V reference voltage in an 180nm CMOS technology.

Gopal Agarwal

Papers

New technique to improve transient response of LDO regulators without an off-chip capacitor