Gopal Dutt

Bio: Gopal Dutt is an academic researcher. The author has contributed to research in topics: VHDL & Field-programmable gate array. The author has an hindex of 1, co-authored 1 publications receiving 8 citations.

HSTL IO Standards Based Processor Specific Green Counter Design on 90nm FPGAAbhay Saxena

Abstract: Extending battery life and increase in portability of modern electronic devices and gadgets are the main motives behind the Green Computing which is also known by similar terms like energy efficient design or low power design or green design. Such efficiency is only possible if all the components of processor are also energy efficient. In this work, the researchers tried to analyze the energy optimization possibility in counter design by selection of energy efficient IO standards. The researchers had used High Speed Transceiver Logic for the purpose of energy efficient counter design on Spartan3 (90nm) FPGA (field-programmable gate array) using VHDL (VHSIC Hardware Description Language) hardware description language along with the Xilinx ISE simulator for the analysis and synthesis of counters. Spartan 3 with 90 nm low power is used to achieve substantial power savings. Here, researchers have used five different HSTL IO standards for this work. The standards used are HSTL_I, HSTL_III, HSTL_III_18, HSTL_III_DCI and HSTL_II_18. With these sets of IO standards, Researchers had run their counter design on various device operating frequencies (1.0 GHz to 4.0 GHz). The results clearly indicate that this dynamic frequency (1.0 GHz in lieu of 4.0 GHz) scaling had saved 45% of total power.

Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA

Abstract: FIR Filter always remains in linear phase with the help of symmetric coefficient. This feature makes it ideal for phase-sensitive applications like data communications. Design of FIR filter with energy efficiency makes excellent sense to achieve energy efficiency in digital selected frequency module of communication. We are using scaling of output load from 5000 to 0 pF to show an effect of output load on both on-chip and off-chip power consumption of FIR filter design. 20 nm technology based FVA1156 package and Kintex-7 family ultra-scale FPGA is taken under reconsideration for implementation of our model. With the use of HSTL_II IO standards, there is 84.39 and 92.83% reduction in IOs power when we scale down capacitance from 5000 to 500 and 0 pF respectively. With the use of HSTL_I_18 IO standards, there is 72.48 and 80.13% reduction in total on-chip power when we scale down capacitance from 5000 to 500 and 0 pF respectively. Along with IOs power and total on-chip power, we have also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.

Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA

Abstract: Reducing the power consumption is the main concern in green computing. So here we used capacitance scaling technique on comparator for optimizing the power. We worked with I/O Power & Leakage Power because Clock Power & Signal Power are independent of capacitance scaling. In our work we have scaled down the capacitance from 512pF to 32pF at various fixed frequency. At 1GHz when we scale down the capacitance from 512pF to 32pF then we got 91.26% reduction in total I/O power dissipation. At 10 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.36% reduction in total I/O power dissipation. At 20 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.364% reduction in total I/O power dissipation. At 30 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.3624% reduction in total I/O power dissipation. At 40GHz when we scale down the capacitance from 512pF to 32pF then we got 91.36277% reduction in total I/O power dissipation. This design is implemented on 28 nm Artix7 FPGA.

SSTL Based Energy Efficient FIFO Design for High Performance Processor of Portable Devices

Abstract: for High Performance Processor of Portable Devices Abhay Saxena , Sanjeev Kumar Sharma , Pragya Agarwal Chandrashekhar Patel #4 #1,3,4 Department of Computer Science DSVV Haridwar, India 1 abhaysaxena2009@gmail.com 3 pragyaagarwal30@gmail.com shekharrockin1988@gmail.com *2 JP Institute of Engineering and Technology Meerut, India 2 dean.ar@jpiet.com Abstract— Now days green computing is major research area in the computer science field, where we want to reduce the total power consumption of our device by applying different techniques .Having this concern we have designed our FIFO (First In First Out) circuit and calculated its total power dissipation at different-different families of SSTL with frequency scaling techniques. In this technique we used following (20 GHz, 40GHz, 60 GHz and 80 GHz ) frequency range. In our work first we have worked with SSTL12 and found that when we scaled down the frequency from 80 GHz to 20 GHz 71.55% reduction in total IO power. In second we have worked with SSTL15 and got 74.02% of reduction in total IO power when we reduced frequency from 80 GHz to 20 GHz. In last we worked with SSTL18_I and SSTL18_II and found 74.29% and 74.28% of reduction in total power respectively, when we scaled down the frequency from 80 GHz to 20 GHz. We have designed our FIFO on 28 nm kintex-7 FPGA family

SSTL IO Based WLAN Channel Specific Energy Efficient RAM Design for Internet of Thing

Abstract: Now days in area of computer science Green computing is creating revolution by bringing some new digital component with less power consumption. Our research work is created on this idea. In this paper our objective is to come up with High Performance RAM design for IOT based processor by reducing the power consumption. For calculating total power consumption of FPGA based RAM we used five WLAN frequencies (900 MHz, 2.4GHz, 3.6GHz, 5GHz, 5.6GHz) and calculated Clock, Logic, Signals, IOs, Leakage power at four different IOs standard (SSTL 135, SSTL15, SSTL18_I, SSTL18_II). In experiment we found that if we will use the SSTL135 instead of SSTL18_II IO standard then we can reduced power consumption by 8.69% at 900MHz, 10.74% at 2.4MHz, 11.80% at 3.6MHz, 12.86% at 5MHz and 13.29% at 5.9MHz. We think that the application of this design will definitely help to design in futuristic IOT based processor development.

Designing Power Efficient Fibonacci Generator Using Different FPGA Families

Abstract: In consideration to wireless communication Fibonacci number is used to generate WPA and WPA2 (Wi-Fi Protected Access) key. Here, in our work we have designed green Fibonacci Generator under different FPGA families. Families we taken into consideration is Automotive Artix7, Artix7 and Kintex7. First we have calculated power consumption of our designed at 2Volt & 1GHz frequency and change the capacitance from 5 to 30pf and found there is tiny changes in Artix7and kintex7 Family but got significant changes in Automotive Artix7 around 16.79%. Secondly we have calculated power consumption of our designed at 2Volt & 10 GHz frequency and change the capacitance from 5 to 30pf, and found 41.09%, 13.95% and 38.06% change respectively for Automotive Artix7, Artix7 and Kintex7 FPGA families. Third we have worked with 3V and 1 GHz and got tiny changes with Artix7 and Kintex7 and found error value with Automotive Artix7. Lastly we have worked with 3V and 10 GHz and changed the capacitance from 5 to 30pf, we got 4.7% and 30.10% significant reduction in power consumption for Artix7 and Kintex7 FPGA families but for Automotive Artix7 we again got error value. Keyword Artix7, kentix7, FPGA, Energy Efficient Design