Gordon K. Madson

Bio: Gordon K. Madson is an academic researcher from Fairchild Semiconductor International, Inc.. The author has contributed to research in topics: Trench & Gate oxide. The author has an hindex of 10, co-authored 16 publications receiving 1098 citations.

Power semiconductor devices and methods of manufacture

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Methods of making power semiconductor devices with thick bottom oxide layer

Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film that fills the trench and covers a top surface of the substrate. and etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. The oxide film can be deposited by sub-atmospheric chemical vapor deposition processes, directional Tetraethoxysilate (TEOS) processes, or high density plasma deposition processes that form a thicker oxide at the bottom of the trench than on the sidewalls of the trench.

Method of manufacturing a trench MOSFET using selective growth epitaxy

Abstract: A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e.g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to form an epitaxial layer around and over the oxide pillars. A trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide pillar.

Trenched Shield Gate Power Semiconductor Devices and Methods of Manufacture

Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region. The charge control trench can be lined with a layer of dielectric material and substantially filled with conductive material. The active trench can include a second shield electrode made of conductive material disposed below the first shield electrode. The first conductive layer inside the active trench can form a secondary gate electrode that is configured to be electrically biased to a desired potential. The semiconductor device can also include a Schottky structure formed between the charge control trench and a second adjacent charge control trench.

Method and structure for shielded gate trench FET

Abstract: A shielded gate field effect transistor includes a trench extending into a semiconductor region. A shield electrode is in a lower portion of the trench, and is insulated from the semiconductor region by a shield dielectric. The shield dielectric comprises first and second dielectric layers, the first dielectric layer extending between the second dielectric layer and the semiconductor region. The second dielectric layer comprises a material which during oxidation process inhibits growth of oxide along surfaces of the semiconductor region covered by the second dielectric layer. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper trench sidewalls. A gate electrode is in an upper portion of the trench over the inter-electrode dielectric.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Power semiconductor devices and methods of manufacture

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor device

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Surgical instrument and method for treating female urinary incontinence

Abstract: Described is a surgical instrument and method for treating female urinary stress incontinence. The instrument includes a first curved needle-like element defining in part a curved shaft having a distal end and a proximal, a mesh for implanting into the lower abdomen of a female to provide support to the urethra; a second curved needle element having a proximal end and a distal end, and a coupler for simultaneous attachment to the distal end of the first needle and the distal end of the second needle.

Method for Manufacturing Semiconductor Device

Abstract: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film