Grant Martin

Bio: Grant Martin is an academic researcher from Tensilica. The author has contributed to research in topics: Electronic system-level design and verification & Embedded software. The author has an hindex of 21, co-authored 82 publications receiving 2161 citations. Previous affiliations of Grant Martin include Cadence Design Systems.

Surviving the SOC Revolution: A Guide to Platform-Based Design

Abstract: Authors. Acknowledgments. Preface. 1. Moving to System-on-Chip Design. 2. Overview of the SOC Design Process. 3. Integration Platforms and SOC Design. 4. Function-Architecture Co-Design. 5. Designing Communications Networks. 6. Developing an Integration Platform. 7. Creating Derivative Designs. 8. Analog/Mixed-Signal in SOC Design. 9. Software Design in SOCs. 10. In Conclusion. Index.

High-Level Synthesis: Past, Present, and Future

Abstract: This article presents the history and evolution of HLS from research to industry adoption. The authors offer insights on why earlier attempts to gain industry adoption were not successful, why current HLS tools are finally seeing adoption, and what to expect as HLS evolves toward system-level design.

Overview of the MPSoC design challenge

Abstract: We review the design challenges faced by MPSoC designers at all levels. Starting at the application level, there is a need for programming models and communications APIs that allow applications to be easily re-configured for many different possible architectures without tedious rewriting, while at the same time ensuring efficient production code. Synchronisation and control of task scheduling may be provided by RTOS's or other scheduling methods, and the choice of programming and threading models, whether symmetric or asymmetric, has a heavy influence on how best to control task or thread execution. Debugging MP systems for the typical application developer becomes a much more complex job, when compared to traditional single-processor debug, or the debug of simple MP systems that are only very loosely coupled. The interaction between the system, applications and software views, and processor configuration and extension, adds a new dimension to the problem space. Zeroing in on the optimal solution for a particular MPSoC design demands a multi-disciplinary approach. After reviewing the design challenges, we end by focusing on the requirements for design tools that may ameliorate many of these issues, and illustrate some of the possible solutions, based on experiments.

ESL Design and Verification: A Prescription for Electronic System Level Methodology

Abstract: Visit the authors' companion site! http://www.electronicsystemlevel.com/ - Includes interactive forum with the authors! Electronic System Level (ESL) design has mainstreamed --- it is now an established approach at most of the world's leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with `no links to implementation', ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems. This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption. ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today. Table of Contents CHAPTER 1: WHAT IS ESL? CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT CHAPTER 4: WHAT ARE THE ENABLERS OF ESL? CHAPTER 5: ESL FLOW CHAPTER 6: SPECIFICATIONS AND MODELING CHAPTER 7: PRE-PARTITIONING ANALYSIS CHAPTER 8: PARTITIONING CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG CHAPTER 10: POST-PARTITIONING VERIFICATION CHAPTER 11: HARDWARE IMPLEMENTATION CHAPTER 12: SOFTWARE IMPLEMENTATION CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS APPENDIX: LIST OF ACRONYMS * Provides broad, comprehensive coverage not available in any other such book * Massive global appeal with an internationally recognised author team * Crammed full of state of the art content from notable industry experts

Reliable estimation of execution time of embedded software

Abstract: Estimates of execution time of embedded software play an important role in function-architecture co-design. This paper describes a technique based upon a statistical approach that improves existing estimation techniques. Our approach provides a degree of reliability in the error of the estimated execution time. We illustrate the technique using both control-oriented and computational-dominated benchmark programs.

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

Abstract: Convolutional Neural Networks (CNNs) have emerged as a fundamental technology for machine learning. High performance and extreme energy efficiency are critical for deployments of CNNs, especially in mobile platforms such as autonomous vehicles, cameras, and electronic personal assistants. This paper introduces the Sparse CNN (SCNN) accelerator architecture, which improves performance and energy efficiency by exploiting the zero-valued weights that stem from network pruning during training and zero-valued activations that arise from the common ReLU operator. Specifically, SCNN employs a novel dataflow that enables maintaining the sparse weights and activations in a compressed encoding, which eliminates unnecessary data transfers and reduces storage requirements. Furthermore, the SCNN dataflow facilitates efficient delivery of those weights and activations to a multiplier array, where they are extensively reused; product accumulation is performed in a novel accumulator array. On contemporary neural networks, SCNN can improve both performance and energy by a factor of 2.7x and 2.3x, respectively, over a comparably provisioned dense CNN accelerator.

Interpolation and SAT-based model checking

Abstract: We consider a fully SAT-based method of unbounded symbolic model checking based on computing Craig interpolants. In benchmark studies using a set of large industrial circuit verification instances, this method is greatly more efficient than BDD-based symbolic model checking, and compares favorably to some recent SAT-based model checking methods on positive instances.

Twelve-Month Prevalence of and Risk Factors for Suicide Attempts in the World Health Organization World Mental Health Surveys

Abstract: Objective: Although suicide is a leading cause of death worldwide, clinicians and researchers lack a data-driven method to assess the risk of suicide attempts. This study reports the results of an analysis of a large cross-national epidemiologic survey database that estimates the 12-month prevalence of suicidal behaviors, identifies risk factors for suicide attempts, and combines these factors to create a risk index for 12-month suicide attempts separately for developed and developing countries. Method: Data come from the World Health Organization (WHO) World Mental Health (WMH) Surveys (conducted 2001–2007), in which 108,705 adults from 21 countries were interviewed using the WHO Composite International Diagnostic Interview. The survey assessed suicidal behaviors and potential risk factors across multiple domains, including sociodemographic characteristics, parent psychopathology, childhood adversities, DSM-IV disorders, and history of suicidal behavior. Results: Twelve-month prevalence estimates of suicide ideation, plans, and attempts are 2.0%, 0.6%, and 0.3%, respectively, for developed countries and 2.1%, 0.7%, and 0.4%, respectively, for developing countries. Risk factors for suicidal behaviors in both developed and developing countries include female sex, younger age, lower education and income, unmarried status, unemployment, parent psychopathology, childhood adversities, and presence of diverse 12-month DSMIV mental disorders. Combining risk factors from multiple domains produced risk indices that accurately predicted 12-month suicide attempts in both developed and developing countries (area under the receiver operating characteristic curve = 0.74–0.80). Conclusions: Suicidal behaviors occur at similar rates in both developed and developing countries. Risk indices assessing multiple domains can predict suicide attempts with fairly good accuracy and may be useful in aiding clinicians in the prediction of these behaviors.

Computer-aided design of analog and mixed-signal integrated circuits

Abstract: This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

FPGAs in Industrial Control Applications

Abstract: The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs.