Gregory Doumenis

Bio: Gregory Doumenis is an academic researcher from National and Kapodistrian University of Athens. The author has contributed to research in topics: Computer science & Encoder. The author has an hindex of 7, co-authored 15 publications receiving 155 citations. Previous affiliations of Gregory Doumenis include National Technical University of Athens.

Local and remote management integration for flexible service provisioning to the home

Abstract: Giving the operator the ability to manage in- home devices greatly increases the potential of the cost-efficient provision of new profitable services In this spirit, standardization undertaken by the DSL forum not only addresses remote management of the residential gateway but recently, also extends to in-house devices We propose a solution that bridges remote management specified by CWMP with UPnP, already established inside the home environment This approach will enable providers to remotely configure and manage in-house UPnP-enabled equipment, thus accelerating the deployment of new services We investigate the nature of the two protocols and specify the bridging functionality, taking into consideration scalability and transparency Experimental results support the applicability of the proposed approach, highlight the importance of message filtering, and provide general insight into the interplay intricacies of the particular protocol functions

A real-time motion estimation FPGA architecture

Abstract: A motion estimation architecture allowing the execution of a variety of block-matching search techniques is presented in this paper. The ability to choose the most efficient search technique with respect to speeding up the process and locating the best matching target block leads to the improvement of the quality of service and the performance of the video encoding. The proposed architecture is pipelined to efficiently support a large set of currently used block-matching algorithms including Diamond Search, 3-step, MVFAST and PMVFAST. The proposed design executes the algorithms by providing a set of instructions common for all the block-matching algorithms and a few instructions accommodating the specific actions of each technique. Moreover, the architecture supports the use of different search techniques at the block level. The results and performance measurements of the architecture have been validated on FPGA supporting maximum throughput of 30 frames/s with frame size 1,024 × 768.

Management traffic in emerging remote configuration mechanisms for residential gateways and home devices

Abstract: XML technology is penetrating the network management in the IETF, UPnP, and DSL forum suite of standards and protocols. The advantages of XML are offered at the cost of long byte streams due to XML's inherently verbose nature. The increase in packet size for remote configuration and management can pose problems, if executed in a point-to-multipoint arrangement comprising one automatic configuration server and thousands of home gateways and multimedia devices. We investigate and exploit the repetitive nature of text patterns in typical XML documents as produced by the configuration and management tasks and as coded in SOAP RPCs. The solution mainly comes from application of the Lempel-Ziv compression algorithm, with minimal additions in the proposed DSL Forum standard. Numerical and experimental results support the applicability and advantages of the proposed approach and provide insight on how these are attributable to different layers of the employed protocol stack.

Automating remote configuration mechanisms for home devices

Abstract: We examine the automatic configuration of consumer electronics devices delivering remote services to the home network. This environment has two particular aspects; it addresses a mass market, hence any automated approach for streamlined deployment, operation and scalability is of prime importance; it also relies on standardization due to its high dependency on communication protocols and services. Modern standards in this domain, along with the invocation of state of the art technologies around XML, give a totally new look at old management problems. More importantly, these standards directly and primarily address configuration issues in a structured and comprehensive way. This paper promotes the view that these standardizations work, pursued and presented in text form by the relevant standardization bodies. It also suggests standard-based methodologies and tools for remote configuration, management, life-cycle support and testing of devices. This inherently ensures compliance to the standards and enables a streamlined design, thus facilitating the provisioning and management of services offered to subscribers. Our contribution concerns relevant tool suites covering to some variable extend all of these aspects. We emphasize the logical succession of each consecutive step/tool and draw attention to the fact that the resulting interrelationships originate from a common source (i.e. the TR-069 standard) and reflect generic needs of the user/player in question.

A real-time H.264/AVC VLSI encoder architecture

Abstract: Evolving applications related to video technologies require video encoder and decoder implemented with low cost and achieving real-time performance. In order to meet this demand and targeting especially the applications imposing low VLSI area requirements, the present paper describes a VLSI H.264/AVC encoder architecture performing at real-time. The encoder uses a pipeline architecture and all the modules have been optimized with respect to the VLSI cost. The encoder design complies with the reference software encoder of the standard, follows the baseline profile level 3.0 and it constitutes an IP-core and/or an efficient stand-alone solution. The architecture operates at a maximum frequency of 100 MHz and achieves maximum throughput of 30 frames/s with frame size 1,024 × 768. Results and performance measurements of the entire encoder have been validated on FPGA and VLSI 0.18 μm occupying a total area of 3.9 mm2.

A Review of Smart Homes—Past, Present, and Future

Abstract: A smart home is an application of ubiquitous computing in which the home environment is monitored by ambient intelligence to provide context-aware services and facilitate remote home control. This paper presents an overview of previous smart home research as well as the associated technologies. A brief discussion on the building blocks of smart homes and their interrelationships is presented. It describes collective information about sensors, multimedia devices, communication protocols, and systems, which are widely used in smart home implementation. Special algorithms from different fields and their significance are explained according to their scope of use in smart homes. This paper also presents a concrete guideline for future researchers to follow in developing a practical and sustainable smart home.

Overview of the H.264 / AVC Video Coding Standard

Abstract: The ITU-T draft H.264 video coding standard has been designed enabling a new generation of digital video applications.While the basic coding framework of the standard is similar to that of currently popular video standard, H.264 includes many coding features not present in earlier standard. We firstly introduces the important features and key techniques in H.264. Then, we presents the performance of it. Study on the new generation ITU-T draft H.264 is of great importance in application field.

On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments

Abstract: Commercial Off-The-Shelf (COTS) processors are now commonly used in real-time embedded systems. The characteristics of these processors fulfill system requirements in terms of time-to-market, low cost, and high performance-per-watt ratio. However, multithreaded (MT) processors are still not widely used in real-time systems because the timing analysis is too complex. In MT processors, simultaneously-running tasks share and compete for processor resources, so the timing analysis has to estimate the possible impact that the inter-task interferences have on the execution time of the applications.In this paper, we propose a method that quantifies the slowdown that simultaneously-running tasks may experience due to collision in shared processor resources. To that end, we designed benchmarks that stress specific processor resources and we used them to (1) estimate the upper limit of a slowdown that simultaneously-running tasks may experience because of collision in different shared processor resources, and (2) quantify the sensitivity of time-critical applications to collision in these resources. We used the presented method to determine if a given MT processor is a good candidate for systems with timing requirements. We also present a case study in which the method is used to analyze three multithreaded architectures exhibiting different configurations of resource sharing. Finally, we show that measuring the slowdown that real applications experience when simultaneously-running with resource-stressing benchmarks is an important step in measurement-based timing analysis. This information is a base for incremental verification of MT COTS architectures.

Field Programmable Gate Array Applications—A Scientometric Review

Abstract: Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.