Guo Ao

Bio: Guo Ao is an academic researcher. The author has contributed to research in topics: Parasitic element & Test data. The author has an hindex of 3, co-authored 15 publications receiving 23 citations.

A Complete Small-Signal MOSFET Model and Parameter Extraction Technique for Millimeter Wave Applications

Abstract: In this paper, we propose a parameter extraction method for a complete MOSFET small signal equivalent circuit model addressing nearly all the parasitic and non-quasi-static (NQS) effects. Extraction and de-embedding of drain/source/gate series resistances and the substrate network are found to be necessary for obtaining the intrinsic elements of the small-signal equivalent circuit. We demonstrate for the first time, a step-by-step procedure for the extraction and de-embedding of the extrinsic model parameters directly from measurements. As a result, a precise intrinsic parameters derivation in the saturation region is presented. Moreover, for the intrinsic small signal equivalent circuit, a gate drain branch is supplemented in parallel to describe parasitic gate-drain coupling under high frequency up to 60 GHz together with the NQS effects. Finally, the presented parameter extraction method is verified by comparing with the corresponding measurement data from the 40-nm RF CMOS process of Shanghai Huali Microelectronics Corporation.

Modeling method for radio frequency MOS device and test structure

Abstract: The invention provides a modeling method for a radio frequency MOS device and a test structure. Parasitic element values which cannot be removed by an existing de-embedding method are represented by virtue of an auxiliary test structure; the obtained original model of the test structure of the MOS device is corrected by these parasitic element values, so that parasitic factors caused by the test structure of the MOS device are completely removed; and planar propulsion of a de-embedding plane of the MOS device from a metal layer of a first interconnect metal layer to a polysilicon/active region (PA) plane is achieved to obtain a model of an intrinsic MOS device. According to the modeling method for the radio frequency MOS device and the test structure, an intrinsic model and a later parasitic model of the device can be respectively obtained by completely separating the parasitic factors except for the MOS device; building of a physically-based scalable MOS device model is facilitated aiming at the MOS devices with different sizes; the precision of the later model can be improved by a mature later interconnect modeling scheme in the industry; and limitations of the test structure are eliminated during device selection, so that the device selection and layout optimization flexibility is improved.

Modeling method for layout proximity effect of multi-interdigital MOS device

Abstract: The invention provides a modeling method for the layout proximity effect of a multi-interdigital MOS device. The method comprises the following steps: designing a test structure, including a reference device group and a contrast device group for establishing a gate pitch layout proximity effect model; establishing an initial model of a multi-interdigital device without layout proximity effect based on test data of the reference devices, modeling by adopting parallel connection of multiple single-gate MOS devices of which the number is equal to that of interdigital devices; constructing a feature size based on the layout factor related to the gate pitch layout proximity effect of each multi-interdigital MOS device, taking the feature size as a layout factor of the single-gate device in the initial model, and indicating the sum of gate pitch layout proximity effect introduced by all interdigitation of the multi-interdigital device by using the sum of layout proximity effect introduced by all parallel-connected single-gate devices based on the layout factor; and constructing a threshold voltage and mobility correction model according to the feature size, the width and length of single interdigitation and the number of interdigitation to correct the initial model.

Automatic and scalable parametric modeling for 1–100GHz transmission line

Abstract: In this paper, an automatic parameter extraction and scalable modeling method for 1∼100GHz transmission line based on the equivalent-circuit model proposed in [1] is established. The parameters are extracted from electromagnetic simulations which are validated by the measurement date of the devices fabricated on HLMC 40nm RF CMOS process. This method is validated by application to scalable modeling of the coplanar waveguide (CPW) with satisfactory fitting accuracy.

Scalable Modeling for the Coplanar Waveguide Step Discontinuity at Frequency up to 150 GHz

Abstract: In this manuscript, a new lumped equivalent-circuit model is proposed for the simulation of the coplanar waveguide (CPW) step discontinuity within the frequency range of 0 to 150 GHz. With the computer-aided modeling and appropriate parameter extraction method, the parameters can be extracted from electromagnetic (EM) simulations without any optimization. Furthermore, we also make the model scalable. Excellent agreement is obtained between the model data and electromagnetic simulations over a considerable range of frequencies and device geometries, which also verifies the validity of our model.

Generalized Frequency Dependent Small Signal Model for High Frequency Analysis of AlGaN/GaN MOS-HEMTs

Abstract: Traditional lumped small signal equivalent circuit models of AlGaN/GaN metal oxide semiconductor high electron mobility transistors (MOS-HEMTs) are made up of constant valued circuit elements. Such models are unable to capture the high frequency behavior (above 20 GHz) of the device. In this work, a modified small signal equivalent circuit model of AlGaN/GaN MOS-HEMTs is presented. The key feature of the proposed model is that the values of the different circuit elements in the model are considered to be frequency dependent in nature and not constants. The frequency dependent value of each circuit element is mathematically represented using polynomial functions where the coefficients of the functions are determined via a least-square curve fitting approach. This frequency dependent attribute of the circuit element values ensures that the proposed model is very accurate at high frequencies without sacrificing the compactness of the model topology. The accuracy of the proposed model has been verified up to 50 GHz using experimentally measured Y-parameters of AlGaN/GaN MOS-HEMTs having a different gate dielectric and gate length.

Small-Signal Modeling of mm- Wave MOSFET up to 110 GHz in 22nm FDSOI Technology

Abstract: In this paper, a comprehensive analysis on small-signal modeling of mm-wave transistor in 22nm FDSOI technology is presented. The model is constructed based on experimental S-parameters up to 110 GHz of a 22FDX® thick-oxide n-MOSFET and analytical parameter extraction approach. The non-quasi static effect is addressed thoroughly in the equivalent circuit model for high frequency validity. The bias-dependent series source and drain resistances are considered to account for the overlap regions between the gate and the highly doped source/drain regions. In addition, a simple RC network is included at the output to model the innegligible substrate coupling at mm-wave frequencies. Excellent agreements between model prediction and measurement are observed in the interested bandwidth for various bias conditions.

Extraction method of parasitic RC network

Abstract: The invention provides an extraction method of a parasitic RC network. The method comprises the following steps: acquiring a layout comprising multiple devices; defining an auxiliary layer in the layout; defining the parasitic RC region in the auxiliary layer; establishing a connection relation between the parasitic RC region and a port of the device; extracting the parasitic resistor and the parasitic capacitor in the parasitic RC region, and computing the parameters of the parasitic resistor and the parasitic capacitor. In the extraction method provided by the invention, the parasitic impedance in a substrate is extracted, and the accuracy of the circuit design is improved.