Guy M. Cohen

Bio: Guy M. Cohen is an academic researcher from IBM. The author has contributed to research in topics: Nanowire & Layer (electronics). The author has an hindex of 41, co-authored 220 publications receiving 4905 citations. Previous affiliations of Guy M. Cohen include KLA-Tencor & GlobalFoundries.

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

Abstract: We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I DSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V DD = 1 V and off-current I OFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

Abstract: We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.

Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs

Abstract: Experimental data from undoped-body gate-all-around (GAA) silicon nanowire (NW) MOSFETs with different sizes demonstrate the universality of short-channel effects as a function of LEFF/λ, where LEFF is the effective channel length and λ is the electrostatic scaling length. Data from undoped-body single-gate extremely thin SOI (ETSOI) devices additionally show that the universality of short-channel effects is valid for any undoped-body fully depleted SOI MOSFET. Our data indicate that LEFF of undoped GAA NW MOSFETs can be scaled down by ~2.5 times compared with undoped single-gate ETSOI MOSFETs while maintaining equivalent short-channel control.

Nanowire field-effect transistors

Abstract: A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.

Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates

Abstract: A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Phase Change Memory

Abstract: In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

Phase-change memory

Abstract: A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.

Band filling with free charge carriers in organometal halide perovskites

Abstract: Femtosecond transient absorption spectroscopy measurements indicate that the dominant relaxation pathway for excited states in perovskite materials is by recombination of free electrons and holes.

Three-dimensional integrated circuits

Abstract: Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 108 vias/cm2), and extremely aggressive wafer-to-wafer alignment (submicron) capability.