H. A. Elgomati

Bio: H. A. Elgomati is an academic researcher from National University of Malaysia. The author has contributed to research in topics: Threshold voltage & NMOS logic. The author has an hindex of 7, co-authored 20 publications receiving 118 citations.

Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor

Abstract: In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.

Application of Taguchi Method in the Optimization of Process Variation for 32nm CMOS Technology.

Abstract: In this paper, we investigate the effect of four process parameters namely HALO implantation, compensation implantations, SiO2 thickness and silicide annealing time on threshold voltage (VTH) in complementary metal oxide semiconductor (CMOS) technology. The setting of process parameters were determined by Taguchi method in experimental design. The influence of the main process parameters on threshold voltage were determined using analysis of variance (ANOVA). The fabrication processes of the transistor were performed by a simulator namely ATHENA. The electrical characterization of the device was done by the a simulator of ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizing process parameters. The other two parameter used in this experiments were Source/Drain (S/D) implantation dose and, silicide annealing temperature Threshold voltage (Vth) results were used as the evaluation parameters. The results show that the VTH value of 0.10308V and -0.10319V for NMOS and PMOS respectively. As conclusion, by utilizing Taguchi Method shown that process parameters can adjust threshold voltage (V TH ) to a stable value of 0.103V that is well within ITRS prediction for 32nm transistor

Modelling of Process Parameters for 32nm PMOS Transistor Using Taguchi Method

Abstract: As CMOS technology scales down to the nanometer level process variation can produce deviation in device parameters which affect circuit performance. In this paper, we investigate the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transistor. Using Taguchi's experimental robust design strategy seven process parameters were assigned to 7 columns of the L18 orthogonal array to conduct 18 simulation runs. Fabrication of the 32nm PMOS transistor was simulated by using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. These simulators were used for computing Vth simulations for each row of the L18 array with 4 combinations of the 2 noise factors. Taguchi's nominal-the-best S/N ratio was used as the objective functions for the minimization of variance in Vth. The best settings of process parameters were determined using Analysis of Mean (ANOM) and Analysis of Variance (ANOVA) for reducing the variability of Vth. The best settings were used for verification simulations and the results showed that the Vth values had the least variance and the mean value could be adjusted to-0.103V +-0.003 for PMOS, which is well within ITRS specifications.

Scaling down of the 32 nm to 22 nm gate length NMOS transistor

Abstract: In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO 2 ) was used as the high-k material and tungsten silicide (WSi x ) was used as the metal gate instead of SiO 2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (V th ) and leakage currents (I on and I off ) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work.

Harnessing voltage margins for energy efficiency in multicore CPUs

Abstract: In this paper, we present the first automated system-level analysis of multicore CPUs based on ARMv8 64-bit architecture (8-core, 28nm X-Gene 2 micro-server by AppliedMicro) when pushed to operate in scaled voltage conditions. We report detailed system-level effects including SDCs, corrected/uncorrected errors and application/system crashes. Our study reveals large voltage margins (that can be harnessed for energy savings) and also large $V_{min}$ variation among the 8 cores of the CPU chip, among 3 different chips (a nominal rated and two sigma chips), and among different benchmarks.Apart from the $V_{min}$ analysis we propose a new composite metric (severity) that aggregates the behavior of cores when undervolted and can support system operation and design protection decisions. Our undervolting characterization findings are the first reported analysis for an enterprise class 64-bit ARMv8 platform and we highlight key differences with previous studies on x86 platforms. We utilize the results of the system characterization along with performance counters information to measure the accuracy of prediction models for the behavior of benchmarks running in particular cores. Finally, we discuss how the detailed characterization and the prediction results can be effectively used to support design and system software decisions to harness voltage margins for energy efficiency while preserving operation correctness. Our findings show that, on average, 19.4% energy saving can be achieved without compromising the performance, while with 25% performance reduction, the energy saving raises to 38.8%.CCS CONCEPTS• Hardware → Power and energy → Power estimation and optimization; • Hardware → Robustness → Hardware reliability → Process, voltage and temperature variations

Chemical Modifications of Cassava Peel as Adsorbent Material for Metals Ions from Wastewater

Abstract: Residues from the processing of cassava roots (Manihot esculenta Crantz), or cassava peels, are evaluated as chemically modified adsorbents with H2O2, H2SO4, and NaOH, in the removal of metal ions Cd(II), Pb(II), and Cr(III) from contaminated water. Modified adsorbents were chemically characterized for their chemical composition and (point of zero charge), while adsorption tests determined the best conditions of pH, adsorbent mass, and contact time between adsorbent and adsorbate in the process of removal of the metal ions. Isotherms obtained from the preliminary results were linearized by Langmuir’s and Freudlich’s models. The thermodynamic parameters, such as , , and , were also evaluated. The modifying solutions proposed were effective in the modification of adsorbents and resulted in high capacity sorption materials. Equilibrium time between adsorbent and adsorbate for the solutions contaminated with metals is about 40 minutes. The Langmuir model adjusted to most results, indicating monolayers adsorption of Cd(II), Pb(II), and Cr(III). The values obtained for Langmuir show a higher adsorption capacity caused by chemical modifications, with values such as 19.54 mg Cd(II) per g of M. NaOH, 42.46 mg of Pb(II) per g of M. NaOH, and 43.97 mg of Cr(III) per g of M H2O2. Results showed that modified cassava peels are excellent adsorbent, renewable, high availability, and low-cost materials and a feasible alternative in the removal of metals in industries.

Materials Processing Technology

Abstract: : The objectives of this program were: (1) to investigate and determine the processing conditions required to achieve desired microstructures and mechanical properties in advanced aerospace materials, (2) to implement and use analytical models for process design in the Materials Processing Laboratory, (3) to validate analytical models by physical modeling, and (4) to create a center of excellence for materials processing. Primary emphasis was given to composites and high temperature materials used in advanced engines and structures. Materials of various types and compositions were studied. In several cases, a full fledged Processing Science approach was utilized, in which the material was fully characterized in terms of microstructural and flow behavior, the proposed processing method was modeled analytically, the actual processing was carried out in the Materials Processing Laboratory (MPL) and the analytical model was validated with experimental measurements. In other cases some of these steps were eliminated when the material or process was well understood.

Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor

Abstract: In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.