In this article, a new low-power multiple-input, single-output (MISO) multi-mode universal biquad operational transconductance amplifier-capacitor (OTA-C) filter with a minimum number of active and passive components is proposed. The proposed filter employs three OTAs, one inverter and two grounded capacitors. The proposed filter can realise all filter frequency responses including low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) in all operation modes including voltage, current, tranasresistance and transconductance modes using the same topology. Furthermore, sensitivity analysis is done which shows that the proposed filter has a low sensitivity to the values of the active and passive elements. The proposed filter is simulated in HSPICE using 0.18 µm CMOS technology. The HSPICE simulation results demonstrate that the proposed filter consumes only 35 μW at 2.5 MHz from a ±0.5 V supply voltage, while all of the transistors are biased in strong inversion region. Also, ...

Design of a new low power MISO multi-mode universal biquad OTA-C filter

An efficient approach for analysis of nonlinear distortion in OTA-C filters with weakly nonlinear transconductors is presented. The procedure is developed based on an algebraic description of a general OTA-C filter structure and, therefore, the results are valid for any filter architecture within OTA-C class. On the basis of the proposed method, explicit formulas for calculating a gain compression-expansion ratio in an arbitrary OTA-C filter are developed. The formulas are easy to implement and use in computer-aided filter design tools. For illustration purposes, several filter structures are considered. The accuracy of the method is verified by comparing the results with the exact values of gain compression-expansion ratio achieved by integrating the differential system that determines the time response of OTA-C filter. The presented approach can be generalized in order to consider other nonlinear parameters. Copyright © 2007 John Wiley & Sons, Ltd.

Analysis of OTA-C filters with weakly nonlinear transconductors

This paper proposes a technique to reduce the capacitance spread in switched-capacitor (SC) filters. The proposed technique is based on a simple charge distribution and partial charge transfer which is applicable to various integrator topologies. An implementation example on an existing integrator topology and a design example of a 2nd-order SC low-pass filter are given to demonstrate the performance of the proposed technique. A design example of an SC filter show that the filter designed using the proposed technique has an approximately 23% less total capacitance than the one of SC low-pass filter with conventional capacitance spread reduction technique.

/pdf/capacitance-reduction-technique-for-switched-capacitor-39tgobrdj8.pdf

Capacitance Reduction Technique for Switched-Capacitor Circuits Based on Charge Distribution and Partial Charge Transfer

This paper presents a CMOS Gm—C complex filter for a low-IF receiver of the IEEE 802.15.4 standard. A pseudo differential OTA with reconfigurable common mode feedback and common mode feed-forward is proposed as well as the frequency tuning method based on a relaxation oscillator. A detailed analysis of non-ideality of the OTA and the frequency tuning method is elaborated. The analysis and measurement results have shown that the center frequency of the complex filter could be tuned accurately. The chip was fabricated in a standard 0.35 μm CMOS process, with a single 3.3 V power supply. The filter consumes 2.1mA current, has a measured in-band group delay ripple of less than 0.16 μs and an IRR larger than 28 dB at 2 MHz apart, which could meet the requirements oftheIEEE802.15.4 standard.

https://iopscience.iop.org/article/10.1088/1674-4926/32/7/075005/pdf

A pseudo differential G m —C complex filter with frequency tuning for IEEE802.15.4 applications

This paper proposes a technique to reduce ca­pacitance spread in switched-capacitor filters. The proposed technique is based on a simple charge distribution and a partial charge transfer techniques, and is applicable to various integrator topologies. Simulation results show that the proposed technique reduces the total capacitance by 70%, which is a significant reduction of filter area. Furthermore, an integrator implemented by the proposed technique is found to be insensitive to parasitic capacitances.

Capacitance spread reduction technique for low-cost switched-capacitor filters implementation

In this paper, a fourth-order, 3.5-MHz, low-pass elliptic Gm-C filter employing low-noise, low-voltage transconductance amplifiers is presented. A new technique to enhance the linearity of the Gm-C filter is proposed. Furthermore, the nonlinear behavior of the filter caused by nonlinear behavior of transconductors with determined input amplitude is discussed. HSpice simulation results of the 1.8-V filter in a 0.18 /spl mu/m CMOS process show a THD of less than -44dB for 0.6V/sub pp/ input signal and an input-referred noise of less than 45 nV//spl radic/Hz in worst case. The current consumption of each OTA is 1.5-mA.

H. Adrang

Papers

A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system