This paper deals with the scheduling analysis of hard real-time streaming applications. These applications are mapped onto a heterogeneous multiprocessor system-on-chip (MPSoC), where we must jointly meet the timing requirements of several jobs. Each job is independently activated and processes streams at its own rate. The dynamic starting and stopping of jobs necessitates the usage of self-timed schedules (STSs). By modeling job implementations using multirate data flow (MRDF) graph semantics, real-time analysis can be performed. Traditionally, temporal analysis of STSs for MRDF graphs only aims at evaluating the average throughput. It does not cope well with latency, and it does not take into account the temporal behavior during the initial transient phase. In this paper, we establish an important property of STSs: the initiation times of actors in an STS are bounded by the initiation times of the same actors in any static periodic schedule of the same job; based on this property, we show how to guarantee strictly periodic behavior of a task within a self-timed implementation; then, we provide useful bounds on maximum latency for jobs with periodic, sporadic, and bursty sources, as well as a technique to check latency requirements. We present two case studies that exemplify the application of these techniques: a simplified channel equalizer and a wireless LAN receiver.

/pdf/self-timed-scheduling-analysis-for-real-time-applications-19jvry4uye.pdf

Self-Timed Scheduling Analysis for Real-Time Applications

Networks-on-chip (NoC) are a scalable interconnect solution to multiprocessor systems on chip (MPSoC). NoCs transport data in packets which are fragments of transactions, such as read and write actions of IPs. For debug purposes, reconstructing transactions at run-time is essential. Run-time analysis of the NoC behavior at transaction level makes the complete MPSoC easier to understand. We present a NoC analyzer able to monitor NoC transactions at run-time. The proposed hardware transaction monitor is able to reconstruct on-chip, at run-time, NoC transactions from bit-level intercepted router link communication. Four NoC analyzer modes are detailed raising the abstraction level gradually from physical raw to logical connection-based, transaction-based and abstract transaction event-based. Each mode is analyzed for area and bandwidth in an experimental setup based on several AEligthereal NoC designs. A transaction monitor has an area cost of 0.026 mm2 in a 0.13 mum CMOS technology, and for several MPEG/audio case studies, the entire monitoring system adds an average of 5% to the NoC area. We show the versatility of our NoC analyzer by run-time monitoring user connections and the Configuration Master IP in the NoC.

/pdf/transaction-monitoring-in-networks-on-chip-the-on-chip-run-18ruwhgj7a.pdf

Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective

Future embedded systems demand multi-processor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semi-automated, time consuming and error prone. In this paper, we present a fully automated design flow to generate communication assist (CA) based multi-processor systems (CA-MPSoC). A worst-case performance model of our CA is proposed so that the performance of the CA-based platform can be analyzed before its implementation. The design flow provides performance estimates and timing guarantees for both hard real-time and soft real-time applications, provided the task to processor mappings are given by the user. The flow automatically generates a super-set hardware that can be used in all use-cases of the applications. The software for each of these use-cases is also generated including the configuration of communication architecture and interfacing with application tasks. CA-MPSoC has been implemented on Xilinx FPGAs for evaluation. Further, it is made available on-line for the benefit of the research community and in this paper, it is used for performance analysis of two real life applications, Sobel and JPEG encoder executing concurrently. The CA-based platform generated by our design flow records a maximum error of 3.4% between analyzed and measured periods. Our tool can also merge use-cases to generate a super-set hardware which accelerates the evaluation of these use-cases. In a case study with six applications, the use-case merging results in a speed up of 18 when compared to the case where each use-case is evaluated individually.

/pdf/ca-mpsoc-an-automated-design-flow-for-predictable-multi-4w7c2s77sm.pdf

CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications

This thesis presents an algorithm that uses a new dataflow model, variable-
rate phased dataflow, to compute buffer capacities that guarantee satisfaction
of timing and resource constraints for task graphs that have inter-task synchro-
nisation behaviour that is dependent on the processed data stream and that
have tasks that are scheduled by run-time schedulers that guarantee resource
budgets. This is an important extension of data
ow analysis techniques, which
allows to model a larger class of applications and allows to include the effects
of a larger class of run-time schedulers. This is exemplified by the case study
with an MP3 playback application, for which we are not aware of alternative
approaches to compute buffer capacities that are sufficient to satisfy the timing
constraints. Furthermore, we improved the accuracy with which the effects of
run-time schedulers that guarantee tasks a minimum resource budget are mod-
elled in data
ow graphs. Instead of capturing the effects of run-time scheduling
using response times, we capture these effects with a model that has a latency
and a rate parameter. Response times do not capture that multiple task exe-
cutions can occur subsequently in the same allocated budget. This is captured
with the model with a latency and a rate parameter, which results in improved
accuracy of the derived bounds on the temporal behaviour. Further, our algo-
rithm has an attractive computational complexity. Every cyclo-static dataflow
graph that is an intuitive model of a task graph is a variable-rate phased dataflow
graph, i.e. every cyclo-static data
ow graph in which no actor has any auto-
concurrency. The algorithm that computes buffer capacities has a polynomial
complexity in the size of the cyclo-static dataflow graph. The validity of our
analysis is confirmed by simulation in both a data
ow simulator as well as in a
cycle-accurate simulator.

/pdf/aperiodic-multiprocessor-scheduling-for-real-time-stream-42ly4tsoj2.pdf

Aperiodic Multiprocessor Scheduling for Real-Time Stream Processing Applications

Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis and quality-of-service techniques. The NoC design problem and the NoC monitoring problem cannot be treated in isolation. We propose a monitoring-aware NoC design flow able to take into account the monitoring requirements in general. We illustrate our flow with a debug driven monitoring case study of transaction monitoring. By treating the NoC design and monitoring problems in synergy, the area cost of monitoring can be limited to 3-20% in general. We also investigate run-time configuration options for the NoC monitoring system resulting in acceptable configuration times.

A monitoring-aware network-on-chip design flow

This paper presents a new multi-core architecture for in-car digital entertainment. Target functions vary from terrestrial reception, digital reception, and compressed audio, up to handsfree voice with acoustic echo cancellation and USB media playback, possibly in different user modes like single versus dual media sound. In the near future, new functions like near field communication, wireless streaming, storage, digital rights management, navigation and video become important. The main challenge is that the platform must be open for future functions, which are unknown at design time. Another challenge is to reduce the design effort by maximizing reuse of hardware and software, especially from related domains like Consumer Electronics (CE). This paper describes an multi-core architecture using a networkon-chip, which provides the required flexibility and scalability. The area overhead, due to the network, is estimated to be 1.5% compared to the current architecture. Furthermore, it is shown that the latency is comparable to the current architecture.

/pdf/a-multi-core-architecture-for-inccar-digital-entertainment-6irnszvisr.pdf

H. Bhullar

Papers

A multi-core architecture for incCar digital entertainment