This paper reviews the fundamentals and latest progress of modeling, analysis, and design technologies for signal integrity and electromagnetic compatibility on PCB and package in the past decades. Most results in this field are based on the very rich and highly educational literature produced by Prof. C. Paul in his long scientific career. The inclusion of parameters variability effects is also considered, and it is demonstrated how statistical simulations can become affordable by means of recently-introduced stochastic methods. Finally, the necessity of practical training of designers is mentioned, and an experience relying on realistic PCB demonstrators is illustrated.

Overview of Signal Integrity and EMC Design Technologies on PCB: Fundamentals and Latest Progress

The symmetric spoof surface plasmon (SSP)-based slow-wave transmission line (SW-TL) with compact transition, low ohmic loss, and low crosstalk between SW-TLs is proposed and investigated. First, the SSP cells are modeled by equivalent circuit elements. The proposed equivalent circuit model is appealing for the integration of SW-TLs with other microwave circuits. With the symmetricity, the SW-TLs are readily realized by a compact mode converter providing gradual impedance, momentum, and polarization matching from guided waves to spoof microwave plasmons. Then, simulation studies and experiments verify that the proposed SSP SW-TL features as low as half the ohmic loss of the traditional counterparts. After that, the low mutual coupling between the proposed SSP SW-TLs is numerically and experimentally substantiated and showed to be up to 10 dB lower than that between conventional microstrip TLs. The proposed low loss, highly isolated and compact SW-TL along with the reliable circuit model enables the further exploitation of promising spoof plasmon modes in microwave technology.

Low-Loss Spoof Surface Plasmon Slow-Wave Transmission Lines With Compact Transition and High Isolation

Innovations in relevant micro-contact areas are highlighted, these include, design, contact resistance modeling, contact materials, performance and reliability. For each area the basic theory and relevant innovations are explored. A brief comparison of actuation methods is provided to show why electrostatic actuation is most commonly used by radio frequency microelectromechanical systems designers. An examination of the important characteristics of the contact interface such as modeling and material choice is discussed. Micro-contact resistance models based on plastic, elastic-plastic and elastic deformations are reviewed. Much of the modeling for metal contact micro-switches centers around contact area and surface roughness. Surface roughness and its effect on contact area is stressed when considering micro-contact resistance modeling. Finite element models and various approaches for describing surface roughness are compared. Different contact materials to include gold, gold alloys, carbon nanotubes, composite gold-carbon nanotubes, ruthenium, ruthenium oxide, as well as tungsten have been shown to enhance contact performance and reliability with distinct trade offs for each. Finally, a review of physical and electrical failure modes witnessed by researchers are detailed and examined.

/pdf/a-review-of-micro-contact-physics-for-microelectromechanical-4z1vzxhmv2.pdf

A review of micro-contact physics for microelectromechanical systems (MEMS) metal contact switches

This paper is intended to provide an expository, physics-based, framework for the estimation of the performance potential and physical scaling limits of resistive memory. The approach taken seeks to provide physical insights into those parameters and physical effects that define device performance and scaling properties. The mechanisms of resistive switching are based on atomic rearrangements in a material. The three model cases are: (1) formation of a continuous conductive path between two electrodes within an insulating matrix, (2) formation of a discontinuous path of conductive atoms between two electrodes within an insulating matrix and (3) rearrangement of charged defects/impurities near the interface between the semiconductor matrix and an electrode, resulting in contact resistance changes. The authors argue that these three model mechanisms or their combinations are representative of the operation of all known resistive memories. The central question addressed in this paper is: what is the smallest volume of matter needed for resistive memory? The two related tasks explored in this paper are: (i) resistance changes due to addition or removal of a few atoms and (ii) stability of a few-atom system.

https://iopscience.iop.org/article/10.1088/0957-4484/22/25/254027/pdf

Scaling limits of resistive memories

The invention is a low-cost, compact radar for adaptively forming beams and independently steering the beams to improve the noise and sensitivity of the radar. The radar includes a printed circuit board, a low-cost multi-layer organic substrate, and a three dimensional (3D) radio frequency (RF) front end that is flood mounted on the substrate.

Three dimensional integrated automotive radars and methods of manufacturing the same

High-frequency transmission lines crosstalk reduction using spacing rules is treated in this paper. Two of the most popular planar transmission line configurations, namely microstrip and stripline, commonly used in printed circuit boards and radio frequency/microwave integrated circuits, are considered in this work. The trace separation between two adjacent transmission lines of each type is stepwise increased as function of the trace width. The single-ended transmission line structures are numerically investigated by a frequency-based 3-D full-wave electromagnetic analysis tool. A particular case using coated microstrip transmission lines has been fabricated, along with some calibration structures, to allow direct measurement and experimental analysis of crosstalk between the single-ended transmission lines. The test structures are characterized at high-frequency (up to 20 GHz) with scattering parameters using a vector network analyzer. The experimental results are compared with the simulation data, and some conclusions and suggestions on the impact and use of spacing rules for high-frequency crosstalk reduction between single-ended transmission lines are presented. These investigations emphasize the necessity of reevaluating classical design rules for their suitability in high-frequency applications.

High-Frequency Transmission Lines Crosstalk Reduction Using Spacing Rules

To be able to reduce the size of products having electronic devices, it becomes more and more important to miniaturize the electromechanical parts of the system. The use of micromechanical connectors and contact structures implies the need of methods for estimating the properties of such devices. This work will, by use of finite element modeling, treat the influence of a thin film constituting at least one of the contacting members of an electrical contact. The error introduced by using the traditional Maxwell/Holm contact constriction resistance theory will be investigated. Numerical methods are used to present a way to approximate the total resistance for the thin metal film contact

Contact resistance of thin metal film contacts

In this paper, the problem of using guard traces for reducing crosstalk between differential transmission line pairs is investigated, both experimentally and by full-wave electromagnetic (EM) simulations. Different cases of differential lines crosstalk are treated with and without guard trace separation between the differential line pairs. Coated microstrip printed circuit board test structures including thru-reflect-line calibration standards are designed and fabricated on a high frequency laminate material, allowing direct measurement of crosstalk between adjacent differential line pairs in the absence and in the presence of guard traces stitched with vias of regular spacing. The test structures are characterized with mixed-mode scattering parameters using a physical layer test system. Different configurations (of differential line pairs) without guard trace, with floating guard traces (which are terminated and nonterminated) and with a solid guard trace separation are investigated using a High Frequency Structure Simulator (a commercial full-wave 3-D EM simulation tool). The experimental data are compared with the simulation results, and some conclusions and guidelines on the effect of guard traces for alleviating crosstalk between differential transmission lines are presented

On The Problem of Using Guard Traces for High Frequency Differential Lines Crosstalk Reduction

To avoid the problem with thermo-mechanical stress induced fatigue using conventional flip-chip mounting of bare chips, an elastic chip socket has been developed. The socket is made by casting silicone elastomer into micro structured silicon molds to form micro bump arrays. After the elastomer is cured and released from the mold, a metal layer is deposited and patterned. A chip is placed in the socket utilizing guiding structures for chip self alignment. The chip is then held in place by a spring loaded back-plate which can also serve as a heat sink for highly effective chip cooling. Since no adhesives, underfills or solders are used, the rework process becomes very simple and it can also be repeated many times for the same socket. Initial contact resistance and thermo-mechanical robustness measurements indicates that this type of sockets could work as a superior replacement for conventional flip-chip technologies in many applications. The particular design of the contact bumps results in metal structures that resemble (although up side down) and are scalable as those in the Chip-First technology. Preliminary thermal shock experiments from room temperature to liquid nitrogen and back show good survival. Thus, this new chip interconnect method indicates the possibility of getting the advantages of the Chip-First technology while eliminating the demand of placing the chip first. The concept will work for chips with rim positioned pads as well as for high density area arrays.

Elastomer chip sockets for reduced thermal mismatch problems and effortless chip replacement, preliminary investigations

The integration of more and more functionality into smaller and smaller form factor electronic products, drives the need for denser chip to substrate interconnect systems. As the number of I/O pins increases, the use of area array chips or packages becomes inevitable. Metal patterned elastomer chip sockets have now been improved to work with contact densities as high as 80 000 contacts/cm/sup 2/ corresponding to a pitch of 36 /spl mu/m. Sockets with 10 000 contacts and a 72-/spl mu/m pitch have survived more than 400 cycles in air-to-air thermal cycling chambers as well as freezing shocks caused by dipping into liquid nitrogen. Although the daisy chain test circuits breaks for temperatures lower than -50/spl deg/C and higher than 90/spl deg/C, they always return to the initial resistance values when entering the normal temperature range. The combination of a gold-to-gold contact interface and the elastic features of the contact bumps makes this socket an ideal compliance layer between bare chips and different types of carrier substrates, reducing the problems caused by thermomechanical mismatch between the substrate and the chip. Bad dies can easily be replaced, since the chip is not soldered or glued to the socket. The size and the possibility to control the geometry of the contacts provides means to maintain a good high-frequency characteristic impedance matching all the way to the chip pad.

H. Hesselbom

Papers

High-Frequency Transmission Lines Crosstalk Reduction Using Spacing Rules

Contact resistance of thin metal film contacts

On The Problem of Using Guard Traces for High Frequency Differential Lines Crosstalk Reduction

Elastomer chip sockets for reduced thermal mismatch problems and effortless chip replacement, preliminary investigations

Very high density interconnect elastomer chip sockets