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Haibo Chen

Researcher at Shanghai Jiao Tong University

Publications -  205
Citations -  6763

Haibo Chen is an academic researcher from Shanghai Jiao Tong University. The author has contributed to research in topics: Computer science & Hypervisor. The author has an hindex of 39, co-authored 176 publications receiving 5452 citations. Previous affiliations of Haibo Chen include Fudan University.

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Proceedings ArticleDOI

CloudVisor: retrofitting protection of virtual machines in multi-tenant cloud with nested virtualization

TL;DR: This paper proposes a transparent, backward-compatible approach that protects the privacy and integrity of customers' virtual machines on commodity virtualized infrastructures, even facing a total compromise of the virtual machine monitor (VMM) and the management VM.
Proceedings ArticleDOI

Corey: an operating system for many cores

TL;DR: This paper proposes three operating system abstractions (address ranges, kernel cores, and shares) that allow applications to control inter-core sharing and to take advantage of the likely abundance of cores by dedicating cores to specific operating system functions.
Proceedings ArticleDOI

PowerLyra: differentiated graph computation and partitioning on skewed graphs

TL;DR: This paper introduces PowerLyra, a new graph computation engine that embraces the best of both worlds of existing graph-parallel systems, by dynamically applying different computation and partitioning strategies for different vertices, and provides an efficient hybrid graph partitioning algorithm (hybrid-cut) that combines edge-cut and vertex-cut with heuristics.
Journal ArticleDOI

PowerLyra: Differentiated Graph Computation and Partitioning on Skewed Graphs

TL;DR: It is argued that skewed distributions in natural graphs also necessitate differentiated processing on high-degree and low-degree vertices, and PowerLyra, a new distributed graph processing system that embraces the best of both worlds of existing graph-parallel systems is introduced.
Proceedings ArticleDOI

Fast in-memory transaction processing using RDMA and HTM

TL;DR: This work presents DrTM, a fast in-memory transaction processing system that exploits advanced hardware features (i.e., RDMA and HTM) to improve latency and throughput by over one order of magnitude compared to state-of-the-art distributed transaction systems.