A 1 V low voltage, low power integer-N frequency synthesizer applied for 2.4 GHz wireless sensor network (WSN) applications is presented. The loop parameters of proposed charge pump phase lock loop frequency synthesizer is calculated and verified on the basis of continuous linear model. The proposed voltage controlled oscillator (VCO) consists of a PMOS cross-coupled transistor pair, a NMOS tail current source and a LC resonator. Common-mode 2nd harmonic filters are employed to improve loaded Q factor and suppress noise. LC resonator is optimized and switched capacitor array is used to lower AM---PM noise conversion. Fabricated in TSMC 0.18 μm CMOS process, the measured phase noise of VCO is ?113.4 dBc/Hz@1 MHz, and ?124.5 dBc/Hz@3.5 MHz while the frequency tuning range covers 4.56---5.32 GHz with 1 V voltage supply. The power dissipation is 2.3 mW and corresponding FOM is about ?185 dBc/Hz. With other blocks of dividers, phase frequency detector, charge pump and auto frequency calibration, the die area of the whole fabricated frequency synthesizer is 1.33 mm2 with pads. With 1 V supply voltage and 9.1 mW power consumption, the measured phase noise of the frequency synthesizer is ?121.9 dBc/Hz@1 MHz and ?134.4 dBc/Hz@3.5 MHz respectively, and the reference spur is ?44.5 dBc. The performance of the designed 1 V integer-N frequency synthesizer is suitable for IEEE 802.15.4/ZigBee based 2.4 GHz WSN applications.

A 1 V 0.18 μm fully integrated integer-N frequency synthesizer for 2.4 GHz wireless sensor network applications

Novel hybrid D/A structures for high-resolution SAR ADCs-analysis, modeling and realization

Investigation on hot-carrier-induced degradation of SOI NLIGBT

A single loop fourth-order delta—sigma modulator is presented for audio applications. A reconfigurable mechanism is adopted for two bandwidth-based modes (8 kHz/16 kHz). Manufactured in the SMIC 0.13 μm CMOS mixed signal process, the chip consumes low power (153.6 μW) and occupies a core area of 0.98 × 0.46 mm2. The presented modulator achieves an 89.3 dB SNR and 90.2 dB dynamic range in 16 kHz mode, as well as a 90.2 dB SNR and 86 dB dynamic range in 8 kHz mode. The designed modulator shows a very competitive figure of merit among state-of-the-art low voltage modulators.

https://iopscience.iop.org/article/10.1088/1674-4926/33/7/075002/pdf

A fourth-order bandwidth-reconfigurable delta—sigma modulator for audio applications

Switched-loop filter for automatically frequency-calibrated phase-locked loops

A high-performance low-power UA analog-to-digital converter (ADC) for digital audio applications is described. It consists of a 2-1 cascaded UA modulator and a decimation filter. Various design optimizations are im- plemented in the system design, circuit implementation and layout design, including a high-overload-level coefficient- optimized modulator architecture, a power-efficient class A/AB operational transconductance amplifier, as well as a multi-stage decimation filter conserving area and power consumption. The ADC is implemented in the SMIC 0.18- m CMOS mixed-signal process. The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm 2 , which dissipates only 2.1 mA quiescent current in the analog circuits.

https://iopscience.iop.org/article/10.1088/1674-4926/31/5/055009/pdf

A high-performance, low-power σ Δ ADC for digital audio applications

A low power and low phase noise phase-locked loop (PLL) design for low voltage (08 V) applications is presented The voltage controlled oscillator (VCO) operates from a 05 V voltage supply, while the other blocks operate from a 08 V supply A differential NMOS-only topology is adopted for the oscillator, a modified precharge topology is applied in the phase-frequency detector (PFD), and a new feedback structure is utilized in the charge pump (CP) for ultra-low voltage applications The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power In addition, several novel design techniques, such as removing the tail current source, are demonstrated to cut down the phase noise Implemented in the SMIC 013 μm RF CMOS process and operated at 08 V supply voltage, the PLL measures a phase noise of-1124 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3166-3383 GHz The improved PFD and the novel CP dissipate 039 mW power from a 08 V supply The occupied chip area of the PFD and CP is 100 × 100 μm2 The chip occupies 063 mm2, and draws less than 654 mW from a 08 V supply

https://iopscience.iop.org/article/10.1088/1674-4926/31/8/085009/pdf

A 0.8 V low power low phase-noise PLL

Degradation behaviors of 20 V NLDMOS operated under off-state avalanche breakdown conditions are presented. A constant current pulse stressing test is applied to the device. Two different degradation mechanisms are identified by analysis of electrical data, technology computer-aided design (TCAD) simulations and charge pumping measurements. The first mechanism is attributed to positive oxide-trapped charges in the N-type drift region, and the second one is due to decreased electron mobility upon interface state formation in the drift region. Both of the mechanisms are enhanced with increasing avalanche breakdown current.

Off-state avalanche breakdown induced degradation in 20 V NLDMOS devices

A CMOS compatible P+/Nwell/Psub double junction photodiode pixel was proposed, which can efficiently detect fluorescence from CsI(Tl) scintillation in an X-ray sensor. Photoelectric and spectral responses of P+/Nwell, Nwell/Psub and P+/Nwell/Psub photodiodes were analyzed and modeled. Simulation results show P+/Nwell/Psub photodiode has larger photocurrent than P+/Nwell photodiode and Nwell/Psub photodiode, and its spectral response is more in accordance with CsI(Tl) fluorescence spectrum. Improved P+/Nwell/Psub photodiode detecting CsI(Tl) fluorescence was designed in CSMC 0.5 μm CMOS process, CTIA (capacitive transimpedance amplifier) architecture was used to readout photocurrent signal. CMOS X-ray sensor IC prototype contains 8 × 8 pixel array and pixel pitch is 100 × 100 μm2. Testing results show the dark current of the improved P+/Nwell/Psub photodiode (6.5 pA) is less than that of P+/Nwell and P+/Nwell/Psub photodiodes (13 pA and 11 pA respectively). The sensitivity of P+/Nwell/Psub photodiode is about 20 pA/lux under white LED. The spectrum response of P+/Nwell/Psub photodiode ranges from 400 nm to 800 nm with a peak at 532 nm, which is in accordance with the fluorescence spectrum of CsI(Tl) in an indirect X-ray sensor. Preliminary testing results show the sensitivity of X-ray sensor IC under Cu target X-ray is about 0.21 Vm2/W or 5097e−/pixel @ 8.05 keV considering the pixel size, integration time and average energy of X-ray photons.

Double junction photodiode for X-ray CMOS sensor IC

The hot-carrier-induced on-resistance degradations of step gate oxide NLDMOS (SG-NLDMOS) transistors are investigated in detail by a DC voltage stress experiment, a TCAD simulation and a charge pumping test. For different stress conditions, degradation behaviors of SG-NLDMOS transistors are analyzed and degradation mechanisms are presented. Then the effect of various doses of n-type drain drift (NDD) region implant on Ron degradation is investigated. Experimental results show that a lower NDD dosage can reduce the hot-carrier induced Ron degradation effectively, which is different from uniform gate oxide NLDMOS (UG-NLDMOS) transistors.

Han Yan

Papers

A high-performance, low-power σ Δ ADC for digital audio applications

A 0.8 V low power low phase-noise PLL

Off-state avalanche breakdown induced degradation in 20 V NLDMOS devices

Double junction photodiode for X-ray CMOS sensor IC

Hot-carrier-induced on-resistance degradation of step gate oxide NLDMOS