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Hans S. Rupprecht

Bio: Hans S. Rupprecht is an academic researcher from IBM. The author has contributed to research in topics: Gallium arsenide & Doping. The author has an hindex of 13, co-authored 31 publications receiving 634 citations.

Papers
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Journal ArticleDOI
Tung-Sheng Kuan1, Philip E. Batson1, Thomas N. Jackson, Hans S. Rupprecht1, E. L. Wilkie1 
TL;DR: In this paper, the interface structures resulting from the alloying reactions between a Au/Ni/Au-Ge composite film and a (100) GaAs substrate were studied by transmission electron microscopy and scanning transmission electron microscope.
Abstract: The interface structures resulting from the alloying reactions between a Au/Ni/Au‐Ge composite film and a (100) GaAs substrate were studied by transmission electron microscopy and scanning transmission electron microscopy. Electron microscope examinations of the cross‐sectional samples prepared in this study offered excellent lateral and depth resolution of local structures which are not available by other analytical techniques used previously in similar studies. The distributions and chemical compositions of various phases formed, and the morphologies of the interfaces between these phases were monitored and compared with the measured contact resistances at three different stages of alloying. A correlation between the interface structure and the contact resistance was found.

225 citations

Patent
03 Mar 1980
TL;DR: An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, is described in this article.
Abstract: An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.

48 citations

Journal ArticleDOI
TL;DR: In this article, a capless annealing technique for GaAs, which utilizes a controlled excess arsenic vapor pressure has been studied, which is about 100 times larger than the arsenic pressure of thermally decomposing GaAs for temperatures of 800-900 °C.
Abstract: A new, capless annealing technique for GaAs, which utilizes a controlled‐excess arsenic vapor pressure has been studied. The excess arsenic vapor is provided by the thermal decomposition of InAs and is about 100 times larger than the arsenic pressure of thermally decomposing GaAs for temperatures of 800–900 °C. This excess pressure forces Si implants to activate predominantly on donor sites for doses of (2–50)×1012 cm−2 studied thus far. A SiF+ dose of 5×1012 cm−2 and implant energy of 250 keV annealed at 900 °C for 30 min produced a sheet electron concentration of 3.5×1012 cm−2 and mobility of 4400 cm2 V−1 sec−1. Photoluminescence studies show that the annealed surfaces must be proximate during anneal to avoid buildup of impurities at the surface. A model based on GaAs evaporation and buildup of bulk impurities on the surface is proposed to explain the results.

47 citations

Patent
12 Jan 1981
TL;DR: In this article, a mesa-type structure is used to construct a bipolar transistor with a small base area and high collector-base capacitance, which is a very important parameter in ultra-high performance integrated circuit devices.
Abstract: A method for device fabrication utilizing a self-aligned process. A combination of advanced semiconductor processing techniques including Deep Dielectric Isolation by reactive-ion etching, etching and refilling, planarizing with oxides and resists, and differential thermal oxidation are used to form devices having small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls which extend from the epitaxial silicon surface through the N+ subcollector region into the P substrate. The width of the deep trench is about 2 μm to 3 μm. A shallow oxide trench extends from the epitaxial silicon surface to the upper portion of the N+ subcollector and separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in a low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which is formed by an etch and refill process and which surrounds the emitter and makes lateral contact to the active base.

34 citations

Patent
Ingrid E. Magdo1, Hans S. Rupprecht1
18 Jan 1980
TL;DR: In this article, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics, and a method for fabricating complementary devices is also provided.
Abstract: Complementary, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics. A method for fabricating such complementary devices is also provided. In the method, a barrier region of a first conductivity type is formed on the surface of the monocrystalline semiconductor substrate doped with a second conductivity type. After an annealing heat treatment to drive in the doping ions of the barrier region, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. The collector region for the other complementary transistor is formed within at least one other isolation region. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. To provide improved PNP transistor performance, the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer.

34 citations


Cited by
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Journal ArticleDOI
TL;DR: The role of extended and point defects, and key impurities such as C, O, and H, on the electrical and optical properties of GaN is reviewed in this article, along with the influence of process-induced or grown-in defects and impurities on the device physics.
Abstract: The role of extended and point defects, and key impurities such as C, O, and H, on the electrical and optical properties of GaN is reviewed. Recent progress in the development of high reliability contacts, thermal processing, dry and wet etching techniques, implantation doping and isolation, and gate insulator technology is detailed. Finally, the performance of GaN-based electronic and photonic devices such as field effect transistors, UV detectors, laser diodes, and light-emitting diodes is covered, along with the influence of process-induced or grown-in defects and impurities on the device physics.

1,693 citations

Journal ArticleDOI
TL;DR: In this article, the authors developed low resistance, refractory ohmic contact materials to n-type GaAs using the deposition and annealing techniques, and it was found that the growth of homo-or hetero-epitaxial intermediate semiconductor layers (ISL) on the GaAs surface was essential for the low resistance Ohmic contact formation.

242 citations

Journal ArticleDOI
TL;DR: The development of high-performance visible-spectrum light-emitting diodes (LEDs) has occurred over a period of over 60 years, beginning with the discovery of the first semiconductor p-n junction in 1940, the development of solid-state electronic band theory in the 1940s, the invention of bipolar transistor in 1947, and the demonstration of efficient light generation from III-V alloys in the 1950s and 1960s.
Abstract: In a practical sense, the development of high-performance visible-spectrum light-emitting diodes (LEDs) has occurred over a period of over 60 years, beginning with the discovery of the first semiconductor p-n junction in 1940, the development of solid-state electronic band theory in the 1940s, the invention of the first bipolar transistor in 1947, and the demonstration of efficient light generation from III-V alloys in the 1950s and 1960s. This paper reviews some of the major scientific and technological developments and observations that have created the materials and device technologies currently used in the commercial mass production of high-brightness visible-spectrum LEDs and that have culminated in white-light sources exhibiting luminous efficacies of over 150 lm/W, far beyond what has been achieved with conventional lighting technologies.

236 citations

Journal ArticleDOI
TL;DR: In this paper, the formation of NiSi films from the reaction of Ni2Si with (100) and (111) silicon substrates was found to be controlled by a lattice diffusion process with an activation energy of 1.70 eV.
Abstract: The formation of NiSi films from the reaction of Ni2Si with (100) and (111) silicon substrates was found to be controlled by a lattice diffusion process with an activation energy of 1.70 eV. In order to correlate kinetic information obtained by Rutherford backscattering with x‐ray diffraction data, ‘‘standard’’ diffraction powder patterns for both Ni2Si and NiSi have been established. The existence of a metastable hexagonal form of NiSi has been confirmed. Observations on the formation of Ni2Si confirm previous investigations. The diffusion process at work during the formation of NiSi is discussed in terms of the crystalline anisotropy of this compound and compared to what is known about diffusion in other silicides.

230 citations

Journal ArticleDOI
TL;DR: In this paper, a low resistance nonalloyed ohmic contact to n−GaAs is formed which utilizes the solid-phase epitaxy of Ge through PdGe, and the conditions necessary to attain low specific contact resistivity (∼10−6 Ω cm2 on 1018 cm−3 n-GaAs) and on the interfacial morphology between the contact metallization and the GaAs substrate.
Abstract: A low resistance nonalloyed ohmic contact to n‐GaAs is formed which utilizes the solid‐phase epitaxy of Ge through PdGe. Discussion focuses on the conditions necessary to attain low specific contact resistivity (∼10−6 Ω cm2 on 1018 cm−3 n‐GaAs) and on the interfacial morphology between the contact metallization and the GaAs substrate. MeV Rutherford backscattering spectrometry and channeling show the predominant reaction to be that of Pd with amorphous Ge to form PdGe followed by the solid‐phase transport and epitaxial growth of Ge on 〈100〉 GaAs. Cross‐sectional transmission electron microscopy and lattice imaging show a very limited initial Pd‐GaAs reaction and a final interface which is planar and structurally abrupt to within atomic dimensions. The presence of excess Ge over that necessary for PdGe formation and the placement of Pd initially in contact with GaAs are required to result in the lowest contact resistivity. The experimental data suggest a replacement mechanism in which an n+‐GaAs surface region is formed when Ge occupies excess Ga vacancies.

195 citations