Hanxing Wang

Bio: Hanxing Wang is an academic researcher from Hong Kong University of Science and Technology. The author has contributed to research in topics: Transistor & Power semiconductor device. The author has an hindex of 12, co-authored 22 publications receiving 527 citations.

Maximizing the Performance of 650-V p-GaN Gate HEMTs: Dynamic RON Characterization and Circuit Design Considerations

Abstract: The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance $R_{{\rm{ON}}}$ and threshold voltage $V_{{\rm{TH}}}$ are evaluated under both static and dynamic (i.e., switching) operating conditions. The dynamic R ON is found to exhibit different dependence on the gate drive voltage $V_{{\rm{GS}}}$ from the static $R_{{\rm{ON}}}$ . While reasonably suppressed at higher $V_{{\rm{GS}}}$ of 5 and 6 V, the degradation in dynamic R ON is significantly larger at lower $V_{{\rm{GS}}}$ of 3–4 V, which is attributed to the positive shift in $V_{{\rm{TH}}}$ under switching operations. In addition to characterization of discrete devices, a custom-designed double-pulse test circuit with 400-V, 10-A test capability is built to evaluate the transient switching performance of the p-GaN gate power transistors. Optimal gate drive conditions are proposed to: 1) provide sufficient gate over-drive to minimize the impact of the $V_{{\rm{TH}}}$ shift on the dynamic $R_{{\rm{ON}}}$ ; and 2) leave enough headroom to save the device from excessive gate stresses. Moreover, gate drive circuit design and board layout considerations are also discussed by taking into account the fast switching characteristics of GaN devices.

Charge Storage Mechanism of Drain Induced Dynamic Threshold Voltage Shift in ${p}$ -GaN Gate HEMTs

Abstract: The drain induced dynamic threshold voltage ( ${V}_{\textrm {th}}$ ) shift of a ${p}$ -GaN gate HEMT with a Schottky gate contact is investigated, and the underlying mechanisms are explained with a charge storage model. When the device experiences a high drain bias ${V}_{\textrm {DSQ}}$ , the gate-to-drain capacitance ( ${C}_{\textrm {GD}}$ ) is charged to ${Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSQ}}$ ). As the drain voltage drops to ${V}_{\textrm {DSM}}$ where ${V}_{\textrm {th}}$ is measured, ${C}_{\textrm {GD}}$ is expected to be discharged to ${Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSM}}$ ). However, the metal/ ${p}$ -GaN Schottky junction could block the discharging current, resulting in storage of negative charges in the ${p}$ -GaN layer. For the device to turn on, additional gate voltage is required to counteract the stored negative charges, resulting in a positive shift of ${V}_{\textrm {th}}$ . The dynamic ${V}_{\textrm {th}}$ shift is an intrinsic and predictable characteristic of the ${p}$ -GaN gate HEMT which is linearly correlated with $\Delta \!{Q}_{\textrm {GD}}={Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSQ}}$ ) $- {Q}_{\textrm {GD}}$ ( ${V}_{\textrm {DSM}}$ ). The ${V}_{\textrm {th}}$ shift is dependent on ${V}_{\textrm {DSQ}}$ as well as ${V}_{\textrm {DSM}}$ , indicating that the ${V}_{\textrm {th}}$ shift is varying along the load line during a switching operation.

An Analytical Model for False Turn-On Evaluation of High-Voltage Enhancement-Mode GaN Transistor in Bridge-Leg Configuration

Abstract: Compared with the state-of-the-art Si-based power devices, enhancement-mode Gallium Nitride (E-mode GaN) transistors have better figures of merit and exhibit great potential in enabling higher switching frequency, higher efficiency, and higher power density for power converters. The bridge-leg configuration circuit, consisting of a controlling switch and a synchronous switch, is a critical component in many power converters. However, owing to the low threshold voltage and fast switching speed, E-mode GaN devices are more prone to false turn-on phenomenon in bridge-leg configuration, leading to undesirable results, such as higher switching loss, circuit oscillation, and shoot through. In order to expand gate terminal's safe operating margin without increasing reverse conduction loss during deadtime, negative gate voltage bias for turn-off and antiparallel diode could be applied to E-mode GaN device. In this paper, with consideration of strong nonlinearities in C–V and I–V characteristics of high-voltage (650 V) E-mode GaN transistors, analytical device models are first developed. Then, we develop an analytical circuit model that combines the circuit parameters with intrinsic characteristics of the high-voltage GaN transistor and antiparallel diode. Thus, key transient waveforms with regard to the false turn-on problem can be acquired, including displacement current and false triggering voltage pulse on gate terminal. The simulated waveforms are then verified on a testing board with GaN-based bridge-leg circuit. In contrast to piecewise switching process models and PSpice simulation, the proposed model exhibits outstanding performances. To provide design guidelines for mitigating false turn-on of GaN transistor, the impacts of different circuit parameters, along with the optimum negative gate voltage bias, are investigated based on the proposed model.

Dynamic Degradation in SiC Trench MOSFET With a Floating p-Shield Revealed With Numerical Simulations

Abstract: A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( ${C}_{rss})$ . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher ${C}_{{{\text {rss}}}}$ and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic ${R}_{{ \mathrm{ON}}}$ during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high ${V}_{{{\text {DS}}}}$ , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high ${V}_{{{\text {DS}}}}$ is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained.

Correction to “Thermally Stable Enhancement-Mode GaN Metal-Isolator-Semiconductor High-Electron-Mobility Transistor With Partially Recessed Fluorine-Implanted Barrier”

Abstract: Al2O3/AlGaN/GaN enhancement-mode metal-isolator-semiconductor high-electron-mobility transistor (MIS-HEMT) featuring a partially recessed (Al) GaN barrier was realized by a fluorine plasma implantation/etch technique. By properly adjusting the RF power driving the fluorine plasma, the fluorine plasma is able to produce two desirable results: 1) a well-controlled slow dry etching for gate recess and 2) implanting fluorine ions into the AlGaN barrier. The fluorine ions become negatively charged in the barrier layer and induce a positive shift in the threshold voltage. The proposed MIS-HEMT exhibits a threshold voltage ( $V_{\mathrm {\mathbf {TH}}})$ of +0.6 V at a drain current of $10~\mu \text{A}$ /mm, a maximum drive current of 730 mA/mm, an ON-resistance of $7.07~\Omega \,\cdot \,$ mm, and an OFF-state breakdown voltage of 703 V at an OFF-state drain leakage current of $1~\mu \text{A}$ /mm. From room temperature to 200 °C, the device exhibits a small negative shift of $V_{\mathrm {\mathbf {TH}}}$ ( $\sim 0.5$ V) that is attributed to the high-quality dielectric/F-implanted-(Al) GaN interface and the partially recessed barrier.

Light-emitting diodes

Abstract: Light-Emitting Diodes. (Monographs in Electrical and Electronic Engineering.) By A. A. Bergh and P. J. Dean. Pp. viii+591. (Clarendon: Oxford; Oxford University: London, 1976.) £22.

GaN-on-Si Power Technology: Devices and Applications

Abstract: In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use.

The 2018 GaN power electronics roadmap

Abstract: Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

Wide Bandgap Devices in AC Electric Drives: Opportunities and Challenges

Abstract: Wide bandgap (WBG) device-based power electronics converters are more efficient and lightweight than silicon-based converters. WBG devices are an enabling technology for many motor drive applications and new classes of compact and efficient motors. This paper reviews the potential applications and advances enabled by WBG devices in ac motor drives. Industrial motor drive products using WBG devices are reviewed, and the benefits are highlighted. This paper also discusses the technical challenges, converter design considerations, and design tradeoffs in realizing the full potential of WBG devices in motor drives. There is a tradeoff between high switching frequency and other issues such as high dv/dt and electromagnetic interference. The problems of high common mode currents and bearing and insulation damage, which are caused by high dv/dt , and the reliability of WBG devices are discussed.