Harshit Agarwal

Bio: Harshit Agarwal is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: BSIM & MOSFET. The author has an hindex of 14, co-authored 62 publications receiving 660 citations. Previous affiliations of Harshit Agarwal include Indian Institute of Technology, Jodhpur & Indian Institute of Technology Kanpur.

BSIM6: Analog and RF Compact Model for Bulk MOSFET

Abstract: BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

Engineering Negative Differential Resistance in NCFETs for Analog Applications

Abstract: In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper.

BSIM-CMG: Standard FinFET compact model for advanced circuit design

Abstract: This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG model's capabilities for circuit design using FinFET transistors for advanced technology nodes.

Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors

Abstract: Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance ( ${C}_{\textsf {fe}}$ ) and the underlying MOS transistor ( ${C}_{\textsf {MOS}}$ ). Since both ${C}_{\textsf {MOS}}$ and ${C}_{\textsf {fe}}$ have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of ${C}_{\textsf {fe}}$ . The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-threshold swing as well as lower power supply ${V}_{\textsf {dd}}$ compared with a prototype single-layer negative-capacitance field-effect transistor.

BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs

Abstract: We propose a compact model for nanosheet FETs that take the effects of quantum confinement into account. The model captures the nanosheet width and thickness dependence of the electrostatic dimension, density of states, effective mass, subband energies, and threshold voltages and includes them in the charge calculation, resulting in an accurate terminal charge and current characteristics. The model has been implemented using Verilog-A in the BSIM-CMG framework for all simulations. It has been validated with band-structure calculation-based TCAD simulations as well as measured data. We have also highlighted the significance of quantum mechanical effects on analog and RF performance of the device.

Technical manual : 日本語版

Abstract: All information and recommendations in this technical manual have been supplied to the best of our knowledge, as accurately as possible and updated to reflect the most recent technological developments. We cannot accept any responsibility for recommendations based solely on this document.

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

BSIM6: Analog and RF Compact Model for Bulk MOSFET

Abstract: BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures

Abstract: We present a comprehensive comparison of the two different types of ferroelectric negative capacitance FET (NCFET) structures: metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS). A new segmentation approach is proposed to simulate MFIS NCFET, which correctly takes care of the nonuniformity in potential and horizontal electric field at the ferroelectric–oxide interface. We show that MFMIS NCFET provides a higher ON-current than MFIS NCFET except for the ferroelectrics with very low remnant polarization ( ${P}_{r}$ ) in the high operating voltage regime. We find that this behavior is caused by a reduction or enhancement of the longitudinal electric field in the channel of MFIS structure depending upon ${P}_{r}$ of the ferroelectric and the operating voltage. Moreover, there exists an optimum ${P}_{r}$ which provides maximum ON-current for both the devices. We also find that MFIS NCFET is more prone to hysteresis and starts showing a hysteretic behavior at a lower ferroelectric thickness compared with MFMIS NCFET.