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Hector Daniel Rico-Aniles

Bio: Hector Daniel Rico-Aniles is an academic researcher from New Mexico State University. The author has contributed to research in topics: Low voltage & CMOS. The author has an hindex of 2, co-authored 4 publications receiving 7 citations.

Papers
More filters
Journal ArticleDOI
TL;DR: A low voltage linear transconductor is introduced that operates with ±0.2V supplies and uses 900nA total biasing current and is not affected by the capacitance of the signal source.
Abstract: A low voltage linear transconductor is introduced. The circuit is a pseudo differential architecture that operates with ±0.2V supplies and uses 900nA total biasing current. It employs a floating battery technique to achieve low voltage operation. The transconductor has a 1MHz bandwidth. It exhibits a SNR = 72dB, SFDR = 42dB and THD = 0.83% for a 100mVpp 10kHz sinusoidal input signal. Moreover, stability is not affected by the capacitance of the signal source. The circuit has been validated with a prototype chip fabricated in a 130nm CMOS technology.

11 citations

Journal ArticleDOI
TL;DR: A technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp.
Abstract: This work was supported by a Grant TEC2016-80396-C2 (AEI/FEDER). The work of Hector Daniel Rico-Aniles was supported by the Mexican Consejo Nacional de Ciencia y Tecnologia (CONACYT) through an academic scholarship under Grant 408946.

3 citations

Journal ArticleDOI
TL;DR: A CMOS low-voltage amplifier with approximately constant bandwidth and DC rejection is introduced, based on the cascade of a wide linear input range OTA, an op-amp and a servo-loop with extremely large time constants.
Abstract: A CMOS low-voltage amplifier with approximately constant bandwidth and DC rejection is introduced. The design is based on the cascade of a wide linear input range OTA, an op-amp and a servo-loop with extremely large time constants. It operates with ±0.45V supplies and a power consumption of 0.81mW in 180nm technology. The bandwidth changes only from 9.08MHz to 9.54MHz over a gain range from 1 to 32, it has a 9.8Hz low cutoff frequency and a DC attenuation of 38dBs. DC floating voltage sources are used to keep the gates of all differential pairs at a constant value close to a supply rail in order to operate the amplifier circuit with minimum supply voltage. The proposed circuit has small and large signal figures of merit FOM SS = 5380 (MHz*pF/mW) and FOM LS = 0.0085((V/ns)*pF/mA) for a nominal gain A = 32.

3 citations

Journal ArticleDOI
26 May 2022-Sensors
TL;DR: In this paper , a collision-free path homotopy-based path-planning algorithm applied to planar robotic arms is presented, where the algorithm utilizes Homotopy continuation methods (HCMs) to solve the nonlinear algebraic equations system (NAES).
Abstract: Achieving the smart motion of any autonomous or semi-autonomous robot requires an efficient algorithm to determine a feasible collision-free path. In this paper, a novel collision-free path homotopy-based path-planning algorithm applied to planar robotic arms is presented. The algorithm utilizes homotopy continuation methods (HCMs) to solve the non-linear algebraic equations system (NAES) that models the robot’s workspace. The method was validated with three case studies with robotic arms in different configurations. For the first case, a robot arm with three links must enter a narrow corridor with two obstacles. For the second case, a six-link robot arm with a gripper is required to take an object inside a narrow corridor with two obstacles. For the third case, a twenty-link arm must take an object inside a maze-like environment. These case studies validated, by simulation, the versatility and capacity of the proposed path-planning algorithm. The results show that the CPU time is dozens of milliseconds with a memory consumption less than 4.5 kB for the first two cases. For the third case, the CPU time is around 2.7 s and the memory consumption around 18 kB. Finally, the method’s performance was further validated using the industrial robot arm CRS CataLyst-5 by Thermo Electron.

2 citations

Proceedings ArticleDOI
01 Aug 2019
TL;DR: An ultra-low-voltage low-power amplifier is introduced that operates with a ±0.2V supply and ±190mV linear input range and has a figure of merit of 2.61 MHzpF/µW for a nominal gain A=15.6.
Abstract: An ultra-low-voltage low-power amplifier is introduced. The design is based on the Cherry-Hooper architecture and operates with a ±0.2V supply and ±190mV linear input range. It has an approximately constant bandwidth of 1MHz with a power consumption of 1.7µW. The low-voltage operation is achieved using floating batteries that keep the gates of all differential pairs at a constant value close to the upper rail with large input signal variations. It has a figure of merit of 2.61 MHzpF/µW for a nominal gain A=15.6.

1 citations


Cited by
More filters
Journal ArticleDOI
01 Mar 2021-Sensors
TL;DR: The simulation results are in agreement with the experimental one that confirmed the advantages of the filter and the natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain.
Abstract: This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

19 citations

Journal ArticleDOI
30 Mar 2022-Sensors
TL;DR: In this article , a voltage-mode universal filter and quadrature oscillator were designed for low-frequency biomedical and sensor applications, and it consumes 357.4 nW of power.
Abstract: This paper presents the extremely low-voltage supply of the CMOS structure of a differential difference transconductance amplifier (DDTA). With a 0.3-volt supply voltage, the circuit offers rail-to-rail operational capability. The circuit is designed for low-frequency biomedical and sensor applications, and it consumes 357.4 nW of power. Based on two DDTAs and two grounded capacitors, a voltage-mode universal filter and quadrature oscillator are presented as applications. The universal filter possesses high-input impedance and electronic tuning ability of the natural frequency in the range of tens up to hundreds of Hz. The total harmonic distortion (THD) for the band-pass filter was 0.5% for 100 mVpp @ 84.47 Hz input voltage. The slight modification of the filter yields a quadrature oscillator. The condition and the frequency of oscillation are orthogonally controllable. The frequency of oscillation can also be controlled electronically. The THD for a 67 Hz oscillation frequency was around 1.2%. The circuit is designed and simulated in a Cadence environment using 130 nm CMOS technology from United Microelectronics Corporation (UMC). The simulation results confirm the performance of the designed circuits.

12 citations

Journal ArticleDOI
01 May 2022-Sensors
TL;DR: In this article , a new mixed-mode universal filter based on a differential difference transconductance amplifier (DDTA) was proposed, which can offer four modes of second-order transfer functions into a single topology, namely, voltage mode (VM), current mode (CM), transadmittance-mode (TAM), and transimpedance mode (TIM) transfer functions.
Abstract: This paper presents a new mixed-mode universal filter based on a differential difference transconductance amplifier (DDTA). Unlike the conventional transconductance amplifier (TA), this DDTA has both advantages of the TA and the differential difference amplifier (DDA). The proposed filter can offer four-mode operations of second-order transfer functions into a single topology, namely, voltage-mode (VM), current-mode (CM), transadmittance-mode (TAM), and transimpedance-mode (TIM) transfer functions. Each operation mode offers five standard filtering responses; therefore, at least twenty filtering transfer functions can be obtained. For the filtering transfer functions, the matching conditions for the input and passive component are absent. The natural frequency and the quality factor can be set orthogonally and electronically controlled. The performance of the proposed topology was evaluated by PSPICE simulator using the 0.18 µm CMOS technology from the Taiwan Semiconductor Manufacturing Company (TSMC). The voltage supply was 1.2 V and the power dissipation of the DDTA was 66 µW. The workability of the filter was confirmed through experimental test by DDTA-based LM13600 discrete-component integrated circuits.

9 citations

Journal ArticleDOI
TL;DR: In this paper , an innovative CMOS structure for Differential Difference Transconductance Amplifiers (DDTA) is presented, which uses the multiple-input MOS transistor (MI-MOST), the bulk-driven, self-cascode and partial positive feedback (PPF) techniques.
Abstract: This paper presents an innovative CMOS structure for Differential Difference Transconductance Amplifiers (DDTA). While the circuit operates under extremely low voltage supply 0.5 V, the circuit’s performance is improved thanks to using the multiple-input MOS transistor (MI-MOST), the bulk-driven, self-cascode and partial positive feedback (PPF) techniques. As a result, the DDTA structure is less complex, with high gain of 93 dB, wide input voltage range nearly rail-to-rail, and wide transconductance tunability. As an example of application, a second-order voltage-mode universal filter using three DDTAs and two 6 pF integrated capacitors is presented. The filter is designed such that no matching conditions are required for the input and passive components, and the input signals need not be inverted. The natural frequency and the quality factor can be set orthogonally while the natural frequency can be electronically controlled. The circuit was designed and simulated in Cadence environment using $0.18 \mu \text{m}$ TSMC technology. The simulation results including intensive Monte-Carlo (MC) and process, temperature, voltage (PVT) analysis confirm the stability and the robustness of the design to process, mismatch variation and PVT corners.

9 citations

Journal ArticleDOI
TL;DR: In this article, a new approach to design super class AB operational transconductance amplifiers (OTAs) with enhanced large-signal and small-Signal performance is presented based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region.
Abstract: A new approach to design super class AB operational transconductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOML) of 236 $\text{V}^{-1}$ . To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.

9 citations