Heesang Kim

Bio: Heesang Kim is an academic researcher from Seoul National University. The author has contributed to research in topics: Leakage (electronics) & MOSFET. The author has an hindex of 7, co-authored 9 publications receiving 131 citations.

A novel methodology on tuning work function of metal gate using stacking bi-metal layers

Abstract: We demonstrate that the work function of a metal gate can be varied by inserting a very thin metal layer ("metal A") between a thick metal ("metal B") and the gate dielectric. The flat band voltage (VFB) of the MOS (metal-oxide-semiconductor) capacitor structure can be controlled within the range bounded by metal A and metal B individually, as demonstrated with various stacked bi-metal layers. For continuous thin layers, we speculate that the work function tunability may be due to the drastic change of the electron density in the thin continuous metal layer in direct contact with a bulk metal. This drastic change of electron density results in a larger junction depth than that expected for a bulk metal. Non-uniform thin layers also appear effective for work function tuning as well, and the observed VFB shift is attributed to the metal island formation at the dielectric/metal A interface.

Characterization of an Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage Current of DRAM Cell Transistors

Abstract: An accurate method for extracting the depth and the energy level of an oxide trap from random telegraph noise (RTN) in the gate-induced drain leakage (GIDL) current of a metal-oxide-semiconductor field-effect transistor (MOSFET) is developed, which correctly accounts for variation in surface potential and Coulomb energy. The technique employs trap capture and emission times defined from the characteristics of GIDL. Ignoring this variation in surface potential leads to an error of up to 116% in trap depth for 80-nm technology generation MOSFETs. RTN amplitude as a function of MOSFET drain-gate voltage is also investigated.

Characterization of the Variable Retention Time in Dynamic Random Access Memory

Abstract: To study the relationship between the original leakage current fluctuation and the detected variable retention time (VRT) from the retention test of dynamic random access memory (DRAM), we simulated the real procedure of the VRT measurement of DRAM. By investigating the results of the simulation, we proposed a new effective VRT measurement method based on the comparison between measurement and simulation. In addition, we investigated the characteristics of the VRT phenomenon in DRAM using the VRT characterization method developed in this study.

RTS-like fluctuation in Gate Induced Drain Leakage current of Saddle-Fin type DRAM cell transistor

Abstract: RTS (random telegraph signal)-like fluctuation in Gate Induced Drain Leakage (GIDL) current of Saddle-Fin (S-Fin) type DRAM cell transistor was investigated for the first time. Furthermore, two types of fluctuation which have apparently different τ high (average time duration of high leakage state) to τ low (average time duration of low leakage state) ratio were investigated, and it was found that the energy difference between bistable levels is similar to that of the junction leakage.

Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM

Abstract: To study trap models related to the variable retention time (VRT) phenomenon in dynamic random access memory (DRAM), we derived equations to calculate the data retention time tret of DRAM and the activation energy for two trap models, i.e., the metastable and oxide trap models. Measuring the tret of VRT cells for various bias and temperature conditions, the dependence of activation energy differences in tret on bias at high and low retention states was extracted. Furthermore, the dependence of the electric field on bias at high and low retention states was also extracted. Using those parameters, we successfully distinguished the two types of trap models.

An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

Abstract: DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering with memory requests. These problems are expected to worsen as DRAM density increases.The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell's retention time. In current systems, all DRAM cells are refreshed at the rate required to guarantee the integrity of the cell with the shortest retention time, resulting in unnecessary refreshes for cells with longer retention times. Prior work has proposed to reduce unnecessary refreshes by exploiting differences in retention time among DRAM cells; however, such mechanisms require knowledge of each cell's retention time.In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. Using a temperature-controlled FPGA-based testing platform, we collect retention time information from 248 commodity DDR3 DRAM chips from five major DRAM vendors. We observe two significant phenomena: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where the retention time of some DRAM cells changes unpredictably over time. We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms.

AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems

Abstract: Multirate refresh techniques exploit the non-uniformity in retention times of DRAM cells to reduce the DRAM refresh overheads. Such techniques rely on accurate profiling of retention times of cells, and perform faster refresh only for a few rows which have cells with low retention times. Unfortunately, retention times of some cells can change at runtime due to Variable Retention Time (VRT), which makes it impractical to reliably deploy multirate refresh. Based on experimental data from 24 DRAM chips, we develop architecture-level models for analyzing the impact of VRT. We show that simply relying on ECC DIMMs to correct VRT failures is unusable as it causes a data error once every few months. We propose AVATAR, a VRT-aware multirate refresh scheme that adaptively changes the refresh rate for different rows at runtime based on current VRT failures. AVATAR provides a time to failure in the regime of several tens of years while reducing refresh operations by 62%-72%.

The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study

Abstract: As DRAM cells continue to shrink, they become more susceptible to retention failures. DRAM cells that permanently exhibit short retention times are fairly easy to identify and repair through the use of memory tests and row and column redundancy. However, the retention time of many cells may vary over time due to a property called Variable Retention Time (VRT). Since these cells intermittently transition between failing and non-failing states, they are particularly difficult to identify through memory tests alone. In addition, the high temperature packaging process may aggravate this problem as the susceptibility of cells to VRT increases after the assembly of DRAM chips. A promising alternative to manufacture-time testing is to detect and mitigate retention failures after the system has become operational. Such a system would require mechanisms to detect and mitigate retention failures in the field, but would be responsive to retention failures introduced after system assembly and could dramatically reduce the cost of testing, enabling much longer tests than are practical with manufacturer testing equipment.In this paper, we analyze the efficacy of three common error mitigation techniques (memory tests, guardbands, and error correcting codes (ECC)) in real DRAM chips exhibiting both intermittent and permanent retention failures. Our analysis allows us to quantify the efficacy of recent system-level error mitigation mechanisms that build upon these techniques. We revisit prior works in the context of the experimental data we present, showing that our measured results significantly impact these works' conclusions. We find that mitigation techniques that rely on run-time testing alone [38, 27, 50, 26] are unable to ensure reliable operation even after many months of testing. Techniques that incorporate ECC[4, 52], however, can ensure reliable DRAM operation after only a few hours of testing. For example, VS-ECC[4], which couples testing with variable strength codes to allocate the strongest codes to the most error-prone memory regions, can ensure reliable operation for 10 years after only 19 minutes of testing. We conclude that the viability of these mitigation techniques depend on efficient online profiling of DRAM performed without disrupting system operation.

Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation

Abstract: A process ( 200 ) for making integrated circuits with a gate, uses a doped precursor ( 124, 126 N and/or 126 P) on barrier material ( 118 ) on gate dielectric ( 116 ). The process ( 200 ) involves totally consuming ( 271 ) the doped precursor ( 124, 126 N and/or 126 P) thereby driving dopants ( 126 N and/or 126 P) from the doped precursor ( 124 ) into the barrier material ( 118 ). An integrated circuit has a gate dielectric ( 116 ), a doped metallic barrier material ( 118, 126 N and/or 126 P) on the gate dielectric ( 116 ), and metal silicide ( 180 ) on the metallic barrier material ( 118 ). Other integrated circuits, transistors, systems and processes of manufacture are disclosed.

Characterization of Pt-Ru binary alloy thin films for work function tuning

Abstract: This letter describes materials and electrical characterization of Pt-Ru binary alloy metal gate electrodes for control of the electrode work function. The work function of the Pt-Ru binary alloy system can be tuned over a wide range of 4.8-5.2 eV. The results indicate that the change of film properties, i.e., resistivity, work function, and crystal structure, with composition is consistent with the equilibrium phase diagram and that the work function in the face-centered cubic and hexagonal close-packed single-phase regions is only weakly dependent on composition, whereas a strong dependence is observed in the intermediate compositional range.