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Hei Kam

Bio: Hei Kam is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Logic gate & Relay. The author has an hindex of 19, co-authored 20 publications receiving 1483 citations.

Papers
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Proceedings ArticleDOI
01 Dec 2009
TL;DR: In this paper, a 4-terminal (4T) relay technology is proposed for complementary logic circuit applications, which can mimic the operation of either an n-channel or p-channel MOSFET.
Abstract: A 4-terminal (4T) relay technology is proposed for complementary logic circuit applications. The advantage of the 4T relay design is that it provides a means for electrically adjusting the switching voltage; as a result, a 4T relay can mimic the operation of either an n-channel or p-channel MOSFET. Fabricated 4T relays exhibit good on-state current (I on ≫ 700µA for V DS = 1V) and zero off-state leakage current. Low-voltage switching (≪ 2V) and low switching delay (100ns) are demonstrated by appropriately biasing the body terminal. Endurance exceeds 10 9 on/off cycles without stiction or wear issues. Complementary operation is demonstrated in a functional relay inverter circuit.

161 citations

Journal ArticleDOI
TL;DR: A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.
Abstract: This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.

161 citations

Proceedings ArticleDOI
05 Dec 2005
TL;DR: In this article, an accumulation-mode design for nanometer-scale electromechanical-gate field effect transistors (NEMFETs) is proposed and studied via simulation.
Abstract: An accumulation-mode design for nanometer-scale electromechanical-gate field effect transistors (NEMFETs) is proposed and studied via simulation In the off state, the gate electrode is in contact with the thin gate dielectric and short-channel effects are effectively suppressed In the on state, the gate electrode is separated from the thin gate dielectric so that the threshold voltage VT is dynamically lowered and the transistor drive current I on is enhanced, and gate leakage is eliminated The NEMFET can likely meet performance specifications for low-power applications at 25 nm gate length, and is attractive for scaled supply voltage operation

142 citations

Proceedings ArticleDOI
10 Nov 2008
TL;DR: It is shown that NEM relay-based adders can achieve an order of magnitude or more improvement over CMOS adders with ns-range delays and with no area penalty, and can be achieved at higher throughputs at the cost of increased area.
Abstract: To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nano-electro-mechanical (NEM) relays. A dynamical Verilog-A model of the NEM relay is described and correlated to device measurements. Using this model we explore NEM relay design strategies for digital logic and I/O that can significantly improve the energy efficiency of the whole VLSI system. By exploiting the low effective threshold voltage and zero leakage achievable with these relays, we show that NEM relay-based adders can achieve an order of magnitude or more improvement in energy efficiency over CMOS adders with ns-range delays and with no area penalty. By applying parallelism, this improvement in energy-efficiency can be achieved at higher throughputs as well, at the cost of increased area. Similar improvements in high-speed I/O energy are also predicted by making use of the relays to implement highly energy-efficient digital-to-analog and analog-to-digital converters.

139 citations

01 Jan 2010
TL;DR: A brief history of mechanical computing is provided followed by an overview of the various types of micromechanical switches, with particular emphasis on electromechanical relays since they are among the most promising for IC applications.
Abstract: Power density has grown to be the dominant challenge for continued complementary metal-oxide- semiconductor (CMOS) technology scaling. Together with recent improvements in microrelay design and process tech- nology, this has led to renewed interest in mechanical computing for ultralow-power integrated circuit (IC) applica- tions. This paper provides a brief history of mechanical computing followed by an overview of the various types of micromechanical switches, with particular emphasis on elec- tromechanical relays since they are among the most promising for IC applications. Relay reliability and process integration challenges are discussed. Demonstrations of functional relay logic circuits are then presented, and relay scaling for improved device density and performance is described. Finally, the energy efficiency benefit of a scaled relay technology versus a CMOS technology with comparable minimum dimensions is assessed.

127 citations


Cited by
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Journal ArticleDOI
17 Nov 2011-Nature
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

2,390 citations

Journal ArticleDOI
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material

1,583 citations

Journal ArticleDOI
25 Oct 2010
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

1,389 citations

Proceedings ArticleDOI
03 Jun 2012
TL;DR: Four key approaches are discussed - the four horsemen - that have emerged as top contenders for thriving in the dark silicon age and each class carries with its virtues deep-seated restrictions that requires a careful understanding of the underlying tradeoffs and benefits.
Abstract: Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utilization wall forces designers to ensure that, at any point in time, large fractions of their chips are effectively dark or dim silicon, i.e., either idle or significantly underclocked. As exponentially larger fractions of a chip's transistors become dark, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift is driving a new class of architectural techniques that “spend” area to “buy” energy efficiency. All of these techniques seek to introduce new forms of heterogeneity into the computational stack. We envision that ultimately we will see widespread use of specialized architectures that leverage these techniques in order to attain orders-of-magnitude improvements in energy efficiency. However, many of these approaches also suffer from massive increases in complexity. As a result, we will need to look towards developing pervasively specialized architectures that insulate the hardware designer and the programmer from the underlying complexity of such systems. In this paper, I discuss four key approaches — the four horsemen — that have emerged as top contenders for thriving in the dark silicon age. Each class carries with its virtues deep-seated restrictions that requires a careful understanding of the underlying tradeoffs and benefits.

334 citations