The realization of a digital recording system using partial-response class-IV signaling with maximum-likelihood sequence detection (MLSD) is described. To perform MLSD at the high data rates encountered in recording systems, a simple implementation of the Viterbi detector based on a difference-metric algorithm is developed. Decision-directed schemes for gain control and timing recovery, for tracking variations of the gain and timing phase during data readback, and for fast initial adjustment from a known preamble are presented. The dynamic behavior of the control algorithms was studied by computer simulations. Coding was used to facilitate timing recovery and gain control, to limit the path memory length of the Viterbi detector, and to allow fast and reliable startup of the receiver. The design and properties of rate 8/9 constrained codes are examined. The problem of equalization is addressed, and analog and combined analog/digital filter implementations are developed. A simple adaptive equalizer capable of compensating variations of the recording channel characteristics with track radius and/or head-to-medium distance is described. >

A PRML system for digital magnetic recording

A new theoretical framework is introduced for analyzing the performance of a finite length minimum-mean-square error decision feedback equalizer (MMSE-DFE) in a multi-input multi-output (MIMO) environment. The framework includes transmit and receive diversity systems as special cases and quantifies the diversity performance improvement as a function of the number of transmit/receive antennas and equalizer taps. Fast and parallelizable algorithms for computing the finite-length MIMO MMSE-DFE are presented for three common multi-user detection scenarios.

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The finite-length multi-input multi-output MMSE-DFE

A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s. The chip occupies 0.8-mm/sup 2/ active area, fabricated in 0.35-/spl mu/m CMOS.

A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS

Constrained codes are a key component in digital recording devices that have become ubiquitous in computer data storage and electronic entertainment applications. This paper surveys the theory and practice of constrained coding, tracing the evolution of the subject from its origins in Shannon's classic 1948 paper to present-day applications in high-density digital recorders. Open problems and future research directions are also addressed.

Codes for digital recorders

The Viterbi algorithm, an application of dynamic programming, is widely used for estimation and detection problems in digital communications and signal processing. It is used to detect signals in communication channels with memory, and to decode sequential error-control codes that are used to enhance the performance of digital communication systems. The Viterbi algorithm is also used in speech and character recognition tasks where the speech signals or characters are modeled by hidden Markov models. The article explains the basics of the Viterbi algorithm as applied to systems in digital communication systems, and speech and character recognition. It also focuses on the operations and the practical memory requirements to implement the Viterbi algorithm in real-time. >

Implementing the Viterbi algorithm

A class of partial response systems of the form P n (D) = (1 - D)(1 + D)n, where D is the delay operator and n is a non-negative integer, is described for the spectral shaping of the readback signal to achieve higher recording densities. The properties of the desired response at the detector input are examined. It is shown that the use of higher values of n can result in higher recording densities without excessive noise enhancement, or, equivalently, pulse slimming. The cost for increased density is higher complexity in the required maximum likelihood detector.

A class of partial response systems for increasing storage density in magnetic recording

The use of adaptive equalization to increase storage density is discussed. Adaptive equalization is attractive since it permits a significant reduction in manufacturing costs by allowing a greater component yield due to relaxed tolerances and also permits a reduction in servicing costs because of a reduced need for fine-tuning on the customer's premises. The differences between data storage and data transmission channels are examined. The storage channel's important signal-processing characteristics are described, covering read and write processes, detection methods, and various types of distortion that can occur in storage channels. The use of signal-to-noise ratio as a performance measure is considered. Equalization methods for peak detection and for sampling detection are discussed. Gains in both linear and areal (track) density are addressed. Some of the basic performance advantages of using adaptive equalization are illustrated. The future of communication technology in storage systems is assessed. >

Adaptive equalization in magnetic-disk storage channels

In the realization of Viterbi decoders with finite precision arithmetic, the values of the survivor metrics computed by the add-compare-select (ACS) recursion must remain within a finite numerical range to avoid catastrophic overflow (or underflow) situations. The authors compare several metric normalization techniques which are suitable for VLSI implementations with fixed-point arithmetic. The modulo normalization technique is found to be the most local and uniform approach. An efficient VLSI design of ACS units based on this technique is discussed. The modified comparison rule is found to produce a more efficient ACS architecture than previous results based on subtraction. >

VLSI architectures for metric normalization in the Viterbi algorithm

The relative performance of well-equalized peak detection, partial response, and decision feedback detection in an intertrack-interference (ITI)-dominated noise environment is calculated, showing that it depends heavily on the intertrack interference. It is found that equalized peak detection performs relatively well at low linear density and extreme offtrack positions (e.g. 20%) and that partial response with Viterbi detector performs the best at small offtrack positions. However, overall, the decision feedback equalizer provides the best performance for a given amount of complexity, and its advantages are discussed. Tolerance to offtrack error as a function of linear density and, taking offtrack performance into account, tradeoffs between increasing linear or areal density are addressed. >

Performance of digital magnetic recording with equalization and offtrack interference

In the state-parallel implementation of the Viterbi algorithm, one add-compare-select (ACS) unit is devoted to each state in the treillis. A systematic approach to partitioning, scheduling, and mapping N trellis states to P ACSs, where N>P, is presented here. The area saving of this architecture comes from the reduced number of ACSs and interconnection wires. The design of the ACS, path metric storage, and routing network is discussed in detail. The proposed architecture creates internal parallelism due to the ACS sharing, which can be exploited to increase the throughput rate by pipelining. Consequently, the architecture offers a favorable (smaller) area-time product, compared to the state-parallel implementation. >

https://ir.nctu.edu.tw:443/bitstream/11536/3060/1/A1993LP11800018.pdf

Hemant K. Thapar

Papers

A class of partial response systems for increasing storage density in magnetic recording

Adaptive equalization in magnetic-disk storage channels

VLSI architectures for metric normalization in the Viterbi algorithm

Performance of digital magnetic recording with equalization and offtrack interference

Area-efficient architectures for the Viterbi algorithm. I. Theory