H
Henry Cook
Researcher at University of California, Berkeley
Publications - 19
Citations - 1931
Henry Cook is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: System on a chip & Memory hierarchy. The author has an hindex of 12, co-authored 19 publications receiving 1637 citations.
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Journal ArticleDOI
Single-chip microprocessor that communicates directly using light
Chen Sun,Chen Sun,Mark T. Wade,Yunsup Lee,Jason S. Orcutt,Jason S. Orcutt,Luca Alloatti,Michael Georgas,Andrew Waterman,Jeffrey M. Shainline,Jeffrey M. Shainline,Rimas Avizienis,Sen Lin,Benjamin Moss,Rajesh Kumar,Fabio Pavanello,Amir H. Atabaki,Henry Cook,Albert Ou,Jonathan Leu,Yu-Hsin Chen,Krste Asanovic,Rajeev J. Ram,Milos A. Popovic,Vladimir Stojanovic +24 more
TL;DR: This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.
Proceedings ArticleDOI
CudaDMA: optimizing GPU memory bandwidth via warp specialization
TL;DR: This work proposes an approach for programming GPUs with tightly-coupled specialized DMA warps for performing memory transfers between on-chip and off-chip memories, and presents an extensible API, CudaDMA, that encapsulates synchronization and common sequential and strided data transfer patterns.
Proceedings ArticleDOI
RAMP gold: an FPGA-based architecture simulator for multiprocessors
Zhangxi Tan,Andrew Waterman,Rimas Avizienis,Yunsup Lee,Henry Cook,David A. Patterson,Krste Asanovica +6 more
TL;DR: The RAMP Gold prototype is a high-throughput, cycle-accurate full-system simulator that runs on a single Xilinx Virtex-5 FPGA board, and which simulates a 64-core shared-memory target machine capable of booting real operating systems.
Proceedings ArticleDOI
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
TL;DR: A practical low-overhead dynamic algorithm to control partition sizes is evaluated, and is able to realize the potential performance guarantees of the optimal static approach, while increasing background throughput by an additional 19%.
Proceedings ArticleDOI
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators
Yunsup Lee,Andrew Waterman,Rimas Avizienis,Henry Cook,Chen Sun,Vladimir Stojanovic,Krste Asanovic +6 more
TL;DR: This is the first dual-core processor to implement the open-source RISC-V ISA designed at the University of California, Berkeley and integrates a custom vector accelerator alongside each single-issue in-order scalar core.