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Author

Herman Maes

Other affiliations: Siemens, Alcatel-Lucent
Bio: Herman Maes is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Silicon & EEPROM. The author has an hindex of 47, co-authored 310 publications receiving 10503 citations. Previous affiliations of Herman Maes include Siemens & Alcatel-Lucent.


Papers
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Journal ArticleDOI
TL;DR: In this article, a new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented.
Abstract: A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO 2 interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.

1,249 citations

Journal ArticleDOI
TL;DR: In this paper, a percolation-based model for intrinsic breakdown in thin oxide layers is proposed, which can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q/sub BD/-distribution for ultrathin oxides.
Abstract: In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q/sub BD/-distribution for ultrathin oxides. An important consequence of this large spread is the strong area dependence of the Q/sub BD/ for ultrathin oxides.

600 citations

Journal ArticleDOI
TL;DR: In this article, a charge pumping technique is used to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (e.g., irradiation, hot-carrier, Fowler-Nordheim stress) and to quantify the degradation.
Abstract: It is shown that the charge pumping technique is able not only to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (eg, irradiation, hot-carrier, Fowler-Nordheim stress), but also in several cases to evaluate and to quantify the degradation It is further shown that the technique can be applied to separate the presence of fixed oxide changes due to charge trapping and the generation of interface traps It can be used to analyze degradations that occur uniformly over the transistor channel, as well as strongly localized transistor degradations (eg, for the case of hot-carrier degradations) All possible cases of uniform and nonuniform degradations, for p-channel as well as for n-channel transistors, are described, and for most of them experimental examples are given >

423 citations

Journal ArticleDOI
TL;DR: In this article, the degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model for both channel types using the charge-pumping technique.
Abstract: A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation For n-channel transistors the degradation is mainly caused by the generation of interface traps Only in the region of hole injection (V/sub g/ approximately=V/sub t/) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps The latter are nevertheless generated in comparable amounts as in n-channel transistors Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model >

415 citations

Proceedings ArticleDOI
09 Dec 1990
TL;DR: In this paper, the authors describe the process fabrication and the electrical characteristics of an SOI MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it.
Abstract: Describes the process fabrication and the electrical characteristics of an SOI (silicon-on-insulator) MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it. Device fabrication is simple and necessitates only a single additional mask and etch step, compared to standard SOI processing. The device shows evidence of volume inversion (inversion is observed not only in surface channels, but through the entire thickness of the silicon film). Because of the presence of two channels and because of reduced carrier scattering within the bulk of the silicon film, the transconductance of the 'gate-all-around' device is more than twice that of a conventional SOI device, and its subthreshold slope is nearly 60 mV/decade at room temperature. >

390 citations


Cited by
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Journal ArticleDOI
TL;DR: In this paper, a review of the literature in the area of alternate gate dielectrics is given, based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success.
Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

5,711 citations

Book
Yuan Taur1, Tak H. Ning1
01 Jan 2016
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

2,680 citations

Journal ArticleDOI
TL;DR: It is demonstrated that through a proper understanding and design of source/drain contacts and the right choice of number of MoS(2) layers the excellent intrinsic properties of this 2-D material can be harvested.
Abstract: While there has been growing interest in two-dimensional (2-D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancy due to the lack of a complete picture of their performance potential. The focus of this article is on contacts. We demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2-D material can be harvested. Using scandium contacts on 10-nm-thick exfoliated MoS2 flakes that are covered by a 15 nm Al2O3 film, high effective mobilities of 700 cm2/(V s) are achieved at room temperature. This breakthrough is largely attributed to the fact that we succeeded in eliminating contact resistance effects that limited the device performance in the past unrecognized. In fact, the apparent linear dependence of current on drain voltage had mislead researchers to believe that a truly Ohmic contact had already been achieved, a miscon...

2,185 citations

Journal ArticleDOI
10 Dec 2004-Science
TL;DR: In this paper, the authors detected and imaged electron-spin polarization near the edges of a semiconductor channel with the use of Kerr rotation microscopy, consistent with the predictions of the spin Hall effect.
Abstract: Electrically induced electron-spin polarization near the edges of a semiconductor channel was detected and imaged with the use of Kerr rotation microscopy The polarization is out-of-plane and has opposite sign for the two edges, consistent with the predictions of the spin Hall effect Measurements of unstrained gallium arsenide and strained indium gallium arsenide samples reveal that strain modifies spin accumulation at zero magnetic field A weak dependence on crystal orientation for the strained samples suggests that the mechanism is the extrinsic spin Hall effect

1,999 citations

Journal ArticleDOI
TL;DR: In this paper, the Schottky barrier heights and band offsets for high dielectric constant oxides on Pt and Si were calculated and good agreement with experiment is found for barrier heights.
Abstract: Wide-band-gap oxides such as SrTiO3 are shown to be critical tests of theories of Schottky barrier heights based on metal-induced gap states and charge neutrality levels. This theory is reviewed and used to calculate the Schottky barrier heights and band offsets for many important high dielectric constant oxides on Pt and Si. Good agreement with experiment is found for barrier heights. The band offsets for electrons on Si are found to be small for many key oxides such as SrTiO3 and Ta2O5 which limit their utility as gate oxides in future silicon field effect transistors. The calculations are extended to screen other proposed oxides such as BaZrO3. ZrO2, HfO2, La2O3, Y2O3, HfSiO4, and ZrSiO4. Predictions are also given for barrier heights of the ferroelectric oxides Pb1−xZrxTiO3 and SrBi2Ta2O9 which are used in nonvolatile memories.

1,947 citations