Hidenori Kitai

Bio: Hidenori Kitai is an academic researcher from National Institute of Advanced Industrial Science and Technology. The author has contributed to research in topics: Threshold voltage & Carrier lifetime. The author has an hindex of 6, co-authored 15 publications receiving 96 citations. Previous affiliations of Hidenori Kitai include Electronics Research Center.

1200 V SiC IE-UMOSFET with low on-resistance and high threshold voltage

Abstract: A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at V g =25 V (E ox =3.2 MV/cm) and VG=20V (E ox =2.5 MV/cm), respectively, for the 3mm × 3mm device were 2.4 and 2.8 mΩcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mΩcm2 with a high Vth of 5.9 V.

A superior 15 kV SiC MOSFET with current spreading layer for high-frequency applications

Abstract: In this study, we developed a superior 15 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) with a current spreading layer (CSL) implanted with nitrogen ions. This MOSFET was developed for high-frequency applications. The CSL and junction field-effect transistor (JFET) regions were optimized using device simulations to reduce reverse transfer capacitance without increasing on-resistance. A SiC MOSFET with a CSL and a die with a size of 5 mm × 5 mm was fabricated. We simultaneously obtained a specific on-resistance of 191 mΩ cm2, a blocking voltage of 15.0 kV, and a reverse transfer capacitance of 0.75 pF for a narrow JFET width of 1.2 μm. In addition, threshold voltage shifts were kept within ±0.1 V for 1000 h at a gate voltage of −15 V and at a temperature of 200 °C.

Low on-resistance and fast switching of 13-kV SiC MOSFETs with optimized junction field-effect transistor region

Abstract: In this paper, a 13-kV SiC MOSFET with a retrograde doping profile in junction field-effect transistor (JFET) regions, which were implanted by nitrogen ions with multiple energies, has been developed for power supplies of X-ray generators and electron guns with an accelerating voltage greater than 10 kV. A JFET region was optimized with device simulation to reduce on-resistance. A SiC MOSFET with an optimized JFET region was fabricated with a 5 mm × 5 mm die size. The specific on-resistance (R onA ) was estimated to be 169 mΩ·cm2. The blocking voltage (BV DSS ) of 13.1 kV was obtained at 10 μA/cm2. Owing to a low electric field in the gate oxide (E ox ), a threshold voltage (V th ) shift within ± 0.06 V was achieved at the gate voltage of −15 V (equal to an electric field of −3 MV/cm) and 200 °C for 1000 hours. The dynamic test with inductive load resulted in turn-off and turn-on switching speeds of 75 kV/μs and 114 kV/μs, respectively, for the DC bus voltage of 10 kV at room temperature.

Development of a novel 1200-V-class 4H-SiC implantation-and-epitaxial trench MOSFET with low on-resistance

Abstract: In this paper, we present a newly developed 1200-V-class 4H-SiC implantation-and-epitaxial trench metal–oxide–semiconductor field-effect transistor (IETMOSFET). It uses high-quality p- and n-epitaxial layers for a channel and a trench current spreading layer (TCSL), respectively. It can enhance both channel mobility and bulk mobility for current spreading by avoiding damage and impurity variations caused by ion implantation. The ion implantation and epitaxial techniques developed for existing ion-implantation-and-epitaxial MOSFETs (IEMOSFETs) are herein utilized to protect the trench bottom and a relatively low-doped epitaxial channel layer with high mobility. By optimizing the geometry of p-base regions under a gate trench structure, we obtain a low specific on-resistance (R ON A) of 1.8 mΩ cm2 with a breakdown voltage (BVDSS) above 1200 V.

Analysis of Gate Oxide Nitridation Effect on SiC MOSFETs by Using Hall Measurement and Split C–V Measurement

Abstract: In this study, 4H–SiC inversion layers were experimentally evaluated by Hall and split C–V measurements, and scattering mechanisms related to gate oxide nitridation were analyzed. Three typical samples with different crystal plane directions and gate oxidation conditions were prepared, and their total trap density and Hall mobility were compared. Based on the temperature dependence of the Hall mobility, we found that scattering mechanisms differed for each sample. The sample C-face oxynitride which had a high nitrogen density at the metal–oxide–semiconductor (MOS) interface, showed a similar temperature dependency to that of ionized impurity scattering. This result suggests that high-density nitrogen acts as donors that supply free carriers and cause ionized impurity scattering, just like in a bulk crystal. In addition, the sample C-face wet has lowest influence of the Coulomb scattering because of the lowest temperature dependence of Hall mobility and the lowest total trap density.

Characterization of traps at nitrided SiO2/SiC interfaces near the conduction band edge by using Hall effect measurements

Abstract: The effects of nitridation on the density of traps at SiO2/SiC interfaces near the conduction band edge were qualitatively examined using a simple, newly developed characterization method that utilizes Hall effect measurements and split capacitance–voltage measurements. The results showed a significant reduction in the density of interface traps near the conduction band edge as a result of nitridation, but the interface traps were not completely eliminated by nitridation.

Characterization of Traps at Nitrided SiO 2 / SiC Interfaces near the Conduction Band Edge by using Hall Effect Measurements

Abstract: The effects of nitridation on the density of traps at SiO2/SiC interfaces near the conduction band edge were qualitatively examined using a simple, newly developed characterization method that utilizes Hall effect measurements and split capacitance–voltage measurements. The results showed a significant reduction in the density of interface traps near the conduction band edge as a result of nitridation, but the interface traps were not completely eliminated by nitridation.

Characterization of Traps at Nitrided SiO$_2$/SiC Interfaces near the Conduction Band Edge by using Hall Effect Measurements

Abstract: The effects of nitridation on the density of traps at SiO$_2$/SiC interfaces near the conduction band edge were qualitatively examined by a simple, newly developed characterization method that utilizes Hall effect measurements and split capacitance-voltage measurements. The results showed a significant reduction in the density of interface traps near the conduction band edge by nitridation, as well as the high density of interface traps that was not eliminated by nitridation.

Body PiN diode inactivation with low on-resistance achieved by a 1.2 kV-class 4H-SiC SWITCH-MOS

Abstract: Integration of SBD into SiC-MOSFET is promising to solve body-PiN-diode related problems known such as forward degradation and reverse recovery loss Particularly in lower breakdown-voltage-class SBD-integrated MOSFET, cell pitch reduction has a greater impact on inactivating the body-PiN-diode Here, we developed a novel device called an SBD-wall-integrated trench MOSFET (SWITCH-MOS), in which small cell pitch of 5pm was realized by utilizing trench side walls both for SBD and MOS channel with buried p+ layer The fabricated 12 kV SWITCH-MOS successfully suppressed the forward degradation under extremely high current density condition with low switching loss, low specific on-resistance, and low leakage current

Anisotropic diamond etching through thermochemical reaction between Ni and diamond in high-temperature water vapour.

Abstract: Diamond possesses excellent physical and electronic properties, and thus various applications that use diamond are under development. Additionally, the control of diamond geometry by etching technique is essential for such applications. However, conventional wet processes used for etching other materials are ineffective for diamond. Moreover, plasma processes currently employed for diamond etching are not selective, and plasma-induced damage to diamond deteriorates the device-performances. Here, we report a non-plasma etching process for single crystal diamond using thermochemical reaction between Ni and diamond in high-temperature water vapour. Diamond under Ni films was selectively etched, with no etching at other locations. A diamond-etching rate of approximately 8.7 μm/min (1000 °C) was successfully achieved. To the best of our knowledge, this rate is considerably greater than those reported so far for other diamond-etching processes, including plasma processes. The anisotropy observed for this diamond etching was considerably similar to that observed for Si etching using KOH.