Hideo Miura

Bio: Hideo Miura is an academic researcher from Tohoku University. The author has contributed to research in topics: Thin film & Residual stress. The author has an hindex of 26, co-authored 392 publications receiving 2862 citations. Previous affiliations of Hideo Miura include Fujifilm Holdings Corporation & Renesas Electronics.

Method of manufacturing a semiconductor device

Abstract: A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes

Effect of external stress on polarization in ferroelectric thin films

Abstract: The polarization changes caused by applying mechanical stresses to a lead zirconate titanate (PZT) thin film were investigated. Both the remnant and spontaneous polarizations decreased when the PZT film was loaded with tensile stress. For compressive stresses, the remnant polarization increased, but spontaneous polarization did not change. In fatigue with tensile stress state, the polarization decreased earlier than when there was no stress, which depend on whether or not the initial polarization value was high. Conversely, in fatigue with compressive stress, the initial higher remnant polarization value was maintained compared with the polarization in the unstress condition.

Optical waveguide device

Abstract: An optical waveguide device for coupling an external wave with a guided wave by means of a grating coupler formed on an optical waveguide device which lies on a substrate The grating coupler is further coated with a cladding layer An external wave is transformed into a guided wave after being diffracted by a first grating coupler, and travels along the waveguide to a second grating coupler The guided wave is then subjected to diffraction by means of the second grating coupler, whereupon a minus first-order wave is diffracted only toward the substrate, whilst other waves of higher order are respectively diffracted toward the cladding layer and the substrate The wave diffracted toward the cladding layer is totally reflected from a cladding layer boundary furtherst from the substrate, thereby passing through the substrate The diffracted wave thus reflected interferes with the other wave of the same order diffracted to the substrate, thereby weakening each other

Crystallization-induced stress in silicon thin films

Abstract: Residual stress change in silicon thin films during crystallization of amorphous silicon is discussed experimentally by detecting the wafer curvature change using a scanning laser microscope. The as‐deposited amorphous‐silicon film shows compressive stress of about 200 MPa. During a crystallization reaction at about 650 °C, a large tensile stress of about 1000 MPa develops in the film due to film shrinkage. The final residual stress of polycrystalline film depends on the film formation process.

Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics

Abstract: The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics. In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30 , a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10 . Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

Fast parallel algorithms for short-range molecular dynamics

Abstract: Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Electronic Transport In Mesoscopic Systems

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Three dimensional structure memory

Abstract: A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.