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Author

Hideo Yoshida

Other affiliations: Mitsubishi Electric
Bio: Hideo Yoshida is an academic researcher from Mitsubishi. The author has contributed to research in topics: Decoding methods & Error detection and correction. The author has an hindex of 21, co-authored 72 publications receiving 1359 citations. Previous affiliations of Hideo Yoshida include Mitsubishi Electric.


Papers
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Journal Article•DOI•
TL;DR: The first experimental demonstration of a forward error correction (FEC) for 10-Gb/s optical communication systems based on a block turbo code (BTC) is reported and the ability of the proposed FEC system to achieve a receiver sensitivity of seven photons per information bit when combined with return-to-zero differential phase-shift keying modulation is demonstrated.
Abstract: The first experimental demonstration of a forward error correction (FEC) for 10-Gb/s optical communication systems based on a block turbo code (BTC) is reported. Key algorithms, e.g., extrinsic information, log-likelihood ratio, and soft decision reliability, are optimized to improve the correction capability. The optimum thresholds for a 3-bit soft decider are investigated analytically. A theoretical prediction is verified by experiment using a novel 3-bit soft decision large scale integrated circuit (LSI) and a BTC encoder/decoder evaluation circuit incorporating a 10-Gb/s return-to-zero on-off keying optical transceiver. A net coding gain of 10.1 dB was achieved with only 24.6% redundancy for an input bit error rate of 1.98/spl times/10/sup -2/. This is only 0.9 dB away from the Shannon limit for a code rate of 0.8 for a binary symmetric channel. Superior tolerance to error bursts given by the adoption of 64-depth interleaving is demonstrated. The ability of the proposed FEC system to achieve a receiver sensitivity of seven photons per information bit when combined with return-to-zero differential phase-shift keying modulation is demonstrated.

176 citations

Proceedings Article•DOI•
Kenya Sugihara1, Y. Miyata1, T. Sugihara1, K. Kubo1, Hideo Yoshida1, Wataru Matsumoto1, Takashi Mizuochi1 •
17 Mar 2013
TL;DR: A novel SD-FEC employing the concatenation of a spatially-coupled type irregular LDPC code with a BCH code is proposed, showing an NCG of 12.0 dB at a BER of 10-15 with 25.5% redundancy.
Abstract: We propose a novel SD-FEC employing the concatenation of a spatially-coupled type irregular LDPC code with a BCH code. Numerical simulations show an NCG of 12.0 dB at a BER of 10-15 with 25.5% redundancy.

131 citations

Journal Article•DOI•
TL;DR: The concept of hardware emulation, with a scalable architecture for the FEC decoder boards, is introduced by way of a pipelined architecture and the practical implementation of soft-decision FEC for 100 Gb/s transport systems is developed.
Abstract: Soft-decision-based forward error correction (FEC) and its practical implementation for 100 Gb/s transport systems are discussed. In applying soft-decision FEC to a digital coherent transponder, we address the configuration of the frame structure of the FEC. For dual-polarized multilevel modulation formats, the keys are having the FEC frames constructed individually for each polarization and a multilane distribution architecture to align each frame. We present two types of soft-decision FEC. One is the concatenation of a Reed-Solomon code and a low-density parity-check (LDPC) code with 2-bit soft decision yielding a Q limit of 7.5 dB. The other, even more powerful, is a triple-concatenated FEC, with a pair of concatenated hard-decision-based block codes further concatenated with a soft-decision-based LDPC code for 20.5% redundancy. We expect that the proposed triple-concatenated codes can achieve a Q limit of 6.4 dB and a net coding gain of 10.8 dB at a post-FEC bit error ratio of 10-15. For the practical implementation of soft-decision FEC for 100 Gb/s systems, we developed field-programmable gate array boards to emulate it. The concept of hardware emulation, with a scalable architecture for the FEC decoder boards, is introduced by way of a pipelined architecture.

76 citations

Patent•
Hideo Yoshida1•
21 Oct 1993
TL;DR: An error correction circuit is capable of performing correction errors in data at a high speed as mentioned in this paper, which leads to an improvement in the speed of error correction of the partial data streams performed by the error correction.
Abstract: An error correction circuit is capable of performing correction errors in data at a high speed. A syndrome generator (2) calculates syndromes of RS codes based on partial data streams which are given from a data buffer (1). A received CRC generator (13) performs CRC coding on the partial data streams which are given from a data buffer (1) to thereby obtain received CRCs. An error pattern CRC generator (14) calculates error pattern CRCs of the respective partial data stream based on error patterns which are generated by an error pattern generation circuit (33). Under the control of a control circuit (40), the operations performed by the syndrome generator (2), the received CRC generator (13) and the error pattern CRC generator (14) are carried out at the same time. An improvement in the speed of error correction of the partial data streams performed by the error correction means directly leads to an improvement in the speed of the whole error correction.

70 citations

Patent•
08 Jun 1994
TL;DR: In this paper, a buffer memory divides N data symbols of a data transmission cell into p blocks and stores the p data blocks for each of L cells to form a transmission frame, and a check code generator carries out the error correcting coding in the unit of p blocks in a direction orthogonal to the direction of transmission.
Abstract: It is an object of this invention to carry out error correcting coding for random errors and cell loss effectively and to obtain a transmitter for coding error correction codes and a receiver for decoding error correction codes on a transmission frame which minimizes transmission delay. This apparatus includes several elements. A buffer memory divides N data symbols of a data transmission cell into p blocks and stores the p data blocks for each of L cells to form a transmission frame. A check code generator carries out the error correcting coding in the unit of p blocks in a direction orthogonal to the direction of transmission. A cell composer selects a specific cell of p blocks having N data symbols and generates a transmission cell. A counter appends an identifier to the top of cells in the transmission direction. The cell with the identifier is transmitted after being replaced with a part of the coding cells as requested.

66 citations


Cited by
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Patent•
30 Oct 2007
TL;DR: An analyte monitor includes a sensor, a sensor control unit, and a display unit as discussed by the authors, which is used to display an indication of a level of an analyte, based on the data obtained using the sensor.
Abstract: An analyte monitor includes a sensor, a sensor control unit, and a display unit. The sensor has, for example, a substrate, a recessed channel formed in the substrate, and conductive material disposed in the recessed channel to form a working electrode. The sensor control unit typically has a housing adapted for placement on skin and is adapted to receive a portion of an electrochemical sensor. The sensor control unit also includes two or more conductive contacts disposed on the housing and configured for coupling to two or more contact pads on the sensor. A transmitter is disposed in the housing and coupled to the plurality of conductive contacts for transmitting data obtained using the sensor. The display unit has a receiver for receiving data transmitted by the transmitter of the sensor control unit and a display coupled to the receiver for displaying an indication of a level of an analyte. The analyte monitor may also be part of a drug delivery system to alter the level of the analyte based on the data obtained using the sensor.

1,856 citations

Patent•
02 Sep 1994
TL;DR: In this paper, the authors describe medical diagnosis and monitoring equipment with wireless electrodes (2a...2f) designed to be secured to the skin of the patient, which can be used to detect EEG and ECG signals or to monitor body/berathing movements.
Abstract: The invention concerns medical diagnosis and monitoring equipment with wireless electrodes (2a...2f) designed to be secured to the skin of the patient (3). The electrodes (2a...2f) include, as well as microsensors, a digital transmitter (31) and receiver (30) unit and an antenna (36a). The electrodes (2a...2f) can be used, for instance, to detect EEG and ECG signals or to monitor body/berathing movements, temperature or perspiration. A preferred embodiment has an electrode which incorporates all functions in a semiconductor chip designed as an integrated circuit with the appropriate sensor, sensor-control, frequency-generation, transmitter and receiver units plus a switching control unit. The antenna (36a) can be mounted either in the flexible electrode covering or directly on the chip.

1,135 citations

Patent•
22 Nov 1999
TL;DR: In this article, the authors describe a system and method for communicating voice and data over a packet-switched network that is adapted to coexist and communicate with a legacy PSTN.
Abstract: The present invention describes a system and method for communicating voice and data over a packet-switched network that is adapted to coexist and communicate with a legacy PSTN. The system permits packet switching of voice calls and data calls through a data network from and to any of a LEC, a customer facility or a direct IP connection on the data network. The system includes soft switch sites, gateway sites, a data network, a provisioning component, a network event component and a network management component. The system interfaces with customer facilities (e.g., a PBX), carrier facilities (e.g., a LEC) and legacy signaling networks (e.g., SS7) to handle calls between any combination of on-network and off-network callers. The soft switch sites provide the core call processing for the voice network architecture. The soft switch sites manage the gateway sites in a preferred embodiment, using a protocol such as the Internet Protocol Device Control (IPDC) protocol to request the set-up and tear-down of calls. The gateway sites originate and terminate calls between calling parties and called parties through the data network. The gateway sites include network access devices to provide access to network resources. The data network connects one or more of the soft switch sites to one or more of the gateway sites. The provisioning and network event component collects call events recorded at the soft switch sites. The network management component includes a network operations center (NOC) for centralized network management.

1,024 citations

Journal Article•DOI•
05 Jun 2006
TL;DR: This paper discusses the generation and detection of multigigabit/s intensity- and phase-modulated formats, and highlights their resilience to key impairments found in optical networking, such as optical amplifier noise, multipath interference, chromatic dispersion, polarization-mode dispersion.
Abstract: Fiber-optic communication systems form the high-capacity transport infrastructure that enables global broadband data services and advanced Internet applications. The desire for higher per-fiber transport capacities and, at the same time, the drive for lower costs per end-to-end transmitted information bit has led to optically routed networks with high spectral efficiencies. Among other enabling technologies, advanced optical modulation formats have become key to the design of modern wavelength division multiplexed (WDM) fiber systems. In this paper, we review optical modulation formats in the broader context of optically routed WDM networks. We discuss the generation and detection of multigigabit/s intensity- and phase-modulated formats, and highlight their resilience to key impairments found in optical networking, such as optical amplifier noise, multipath interference, chromatic dispersion, polarization-mode dispersion, WDM crosstalk, concatenated optical filtering, and fiber nonlinearity

772 citations

Patent•
Mohammad Khair1, Richard Ng, Salvador Lopez1, Sanjar Ghaem1, William L. Olson1 •
17 Apr 2001
TL;DR: In this article, a wireless, programmable system for medical monitoring includes a base unit (18) and a plurality of individual wireless, remotely programmable biosensor transceivers (20).
Abstract: A wireless, programmable system for medical monitoring includes a base unit (18) and a plurality of individual wireless, remotely programmable biosensor transceivers (20). The base unit (18) manages the transceivers (20) by issuing registration, configuration, data acquisition, and transmission commands using wireless techniques. Physiologic data from the wireless transceivers (20) are demultiplexed and supplied via a standard interface to a conventional monitor (914) for display. Initialization, configuration, registration, and management routines for the wireless transceivers and the base unit are also described.

672 citations