Hidetoshi Onodera

Bio: Hidetoshi Onodera is an academic researcher from Kyoto University. The author has contributed to research in topics: CMOS & Electronic circuit. The author has an hindex of 27, co-authored 358 publications receiving 3238 citations. Previous affiliations of Hidetoshi Onodera include University of California, Berkeley & Carnegie Mellon University.

Branch-and-bound placement for building block layout

Abstract: We present a branch-and-bound placement technique for building block layout that effectively searches for an optimal placement in the whole solution space. We first describe a block placement problem and its solution space. Then we explain branching and bounding operations designed for the placement problem. Constraints on critical nets and/or the shape of a resulting chip can be taken into account in the search process. Experiments reveals that the number of blocks the method can manage is around six if the whole solution space is explored. For a problem which contains more blocks than the limit, we decompose the problem hierarchically and apply the method to each subproblem. The results for standard benchmark examples and a comparison with those of other systems are given to demonstrate the performance of the method.

Refractive-index measurement of bulk materials: prism coupling method.

Abstract: A simple method of measuring refractive indices of bulk materials using a prism coupling procedure is described. Refractive indices are determined from the measurement of the angle incident to the prism at which total reflection on the prism base breaks. This method is shown to possess the advantages of its simple procedure and sample preparation. The accuracy is comparable with that of minimum deviation method if the prism is well calibrated. Experimental results for several materials are given with an evaluation of possible errors.

Operational-amplifier compilation with performance optimization

Abstract: A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density. >

Manufacturability-Aware Design of Standard Cells

Abstract: We focus our attention on the layout dependent Across Chip Linewidth Variability (ACLV) of gate-forming poly-silicon patterns as a measure for manufacturability, which is a major contributor of systematic gate-length variation. First, we study the ACLV of standard cell layouts by lithography simulation. Then, we introduce regularity in gate-forming poly-silicon patterns and how it improves the ACLV and also how it incurs area-overhead. According to the investigation, we propose two design guidelines for standard-cell layout that can reduce ACLV with reasonable area overhead. Those guidelines include on-grid fixed-pitch layout with dummy-poly insertion and stretched gate-poly extension. Design experiments assuming a 65 nm process technology indicate that a D-FF designed with the first guideline reduces ACLV by 35% with 14% area overhead and the second guideline reduces ACLV by 75% with 29% area overhead at the best focus condition. Under defocus conditions, both layouts exhibit stable characteristics whereas the variability of conventional layout grows rapidly as the level of defocus increases. Circuit-level lithography simulation over benchmark circuits also supports that the proposed guidelines considerably reduces the amount of gate length variation.

An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

Abstract: A layout structure to avoid upsets due to Multiple Cell Upsets (MCUs) is proposed for rad-hard dual-modular Flip-Flops (FFs) called BCDMR (Bistable Cross-coupled Dual-Modular Redundancy) by separating critical components. We have fabricated a 65 nm chip including 30 kbit dual-modular FF arrays on twin-well and triple-well structures. High-energy broad-spectrum neutron irradiations reveal that no soft error is observed up to 100 MHz in the twin-well, but some errors are observed in the triple well. The triple-well structure is sensitive to MCUs because the p-well potential can be easily elevated.

Algorithms for VLSI Physical Design Automation

Abstract: From the Publisher: This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

Abstract: This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.