Hiroki Kawada

Bio: Hiroki Kawada is an academic researcher from Hitachi. The author has contributed to research in topics: Metrology & Charged particle beam. The author has an hindex of 17, co-authored 142 publications receiving 1196 citations.

Semiconductor device manufacturing apparatus and method with optical monitoring of state of processing chamber

Abstract: A semiconductor device manufacturing apparatus and its method, measures the amount or chemical composition of reaction products adhering to or deposited on the inside of a processing chamber of the semiconductor device manufacturing apparatus, without exposing the chamber to the air. External light, such as infrared light, is introduced from a light introducing unit into the processing chamber. A light receiving unit provided outside the processing chamber receives light reflected from a specified location inside the processing chamber or light reflected from an arbitrary location inside the chamber. The received light is then subjected to spectrometry or photometry to judge how badly the chamber is contaminated and to judge the state of the process being carried out.

Characterization of line-edge roughness in resist patterns and estimations of its effect on device performance

Abstract: A guideline for evaluating LER and total procedure to estimate effects of measured LER on device performance were proposed. Spatial-frequency distributions of LER in various resist materials were investigated and general characteristics of spatial-frequency distribution of LER were obtained. Measurement parameters for accurate LER measurement can be calculated according to the guideline. Measured line-width distribution was used for predicting degradation and variation in MOS transistor performance using the 2D device simulation. Effect of long-period component of LER was clarified as well as short-period component.

Metrology of LER: influence of line-edge roughness (LER) on transistor performance

Abstract: The influence of line-edge roughness (LER) on transistor performance was investigated experimentally and the preciously proposed guideline for CD and LER measurements was examined. First, regarding the transistor-performance measurements, a shift of roll-off curves caused by LER within a gate pattern was observed. Moreover, the effect of transistor-width fluctuation originating from long-period LER was found to cause a variation in transistor performance. Second, regarding LER and CD metrology, the previously reported guideline was validated by using KrF and ArF resist-pattern samples. It was found that both CD and LER should be evaluated with the 2-μm-long inspection area. Based on this guideline, a comprehensive approach for evaluating LER and CD for transistor fabrication process is presented. The authors consider that this procedure can provide useful information for the 65-nm-node technology and beyond.

Bias-free measurement of LER/LWR with low damage by CD-SEM

Abstract: We propose a new method for the evaluation of line-edge or linewidth roughness (LER/LWR). Conventional, directly measured LER/LWR values always contain a random noise contribution, which is called LER/LWR bias. Our method can separate this bias artifact from the true LER/LWR by using a single image of the sample pattern. The idea is based on the dependency of a measured LER/LWR value on the image-processing parameter for noise reduction. Both, the conventional and the new bias-free LER were calculated on series of images with different frame integration numbers but a fixed field of view. In addition, the validity of this method to the gate-LWR measurement on an ArF resist line pattern was examined. The LER/LWR obtained by our method was independent of the frame number, and agreed with the conventional LER/LWR as measured on an image with a sufficiently large frame-number. That is, our method can evaluate LER/LWR without random-noise contribution, suggesting that the method can be applied to images recorded under low-sample-damage conditions (i.e., low signal-to-noise ratio). It is concluded that the proposed bias-free LER/LWR measurement method will be a powerful tool in lithography metrology especially for achieving practical and accurate LER/LWR measurement with low sample damage.

Pattern inspection method

Abstract: The present invention may include a pattern inspection method of extracting a pattern edge shape from an image obtained by a scanning microscope and inspecting the pattern A control section and a computer of the scanning microscope process the intensity distribution of reflected electrons or secondary electrons, find the distribution of gate lengths in a single gate from data about edge positions, estimate the transistor performance by assuming a finally fabricated transistor to be a parallel connection of a plurality of transistors having various gate lengths, and determine the pattern quality and grade based on an estimated result In this manner, it is possible to highly, accurately and quickly estimate an effect of edge roughness on the device performance and highly accurately and efficiently inspect patterns in accordance with device specifications

Charged particle beam apparatus

Abstract: A charged particle beam includes: a computer that controls a needle actuating mechanism so as to approach a needle to a sample piece using a template formed from an absorbed current image obtained by irradiating the needle with a charged particle beam and a tip coordinate of the needle acquired from a secondary electron image obtained by irradiating the needle with the charged particle beam.

Metrology for the next generation of semiconductor devices

Abstract: The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.

Method and apparatus for monitoring plasma processing operations

Abstract: The invention generally relates to various aspects of a plasma process, and more specifically the monitoring of such plasma processes. One aspect relates in at least some manner to calibrating or initializing a plasma monitoring assembly. This type of calibration may be used to address wavelength shifts, intensity shifts, or both associated with optical emissions data obtained on a plasma process. A calibration light may be directed at a window through which optical emissions data is being obtained to determine the effect, if any, that the inner surface of the window is having on the optical emissions data being obtained therethrough, the operation of the optical emissions data gathering device, or both. Another aspect relates in at least some manner to various types of evaluations which may be undertaken of a plasma process which was run, and more typically one which is currently being run, within the processing chamber. Plasma health evaluations and process identification through optical emissions analysis are included in this aspect. Yet another aspect associated with the present invention relates in at least some manner to the endpoint of a plasma process (e.g., plasma recipe, plasma clean, conditioning wafer operation) or discrete/discernible portion thereof (e.g., a plasma step of a multiple step plasma recipe). A final aspect associated with the present invention relates to how one or more of the above-noted aspects may be implemented into a semiconductor fabrication facility, such as the distribution of wafers to a wafer production system.

Plasma Processing Apparatus

Abstract: A plasma processing apparatus wherein a layer structure consisting of plural layers formed in stack one upon another on a semiconductor wafer placed on the sample holder located in the process chamber, is etched with plasma generated in the process chamber by supplying high frequency power to the electrode disposed in the sample holder, the apparatus comprising a ring-shaped electrode disposed above the electrode and around the periphery of the top portion of the sample holder, an outer circumferential ring of dielectric material disposed above the ring-shaped electrode and opposite to the plasma, and a power source for supplying power at different values to the ring-shaped electrode depending on the sorts of layers of the layer structure.

Plasma-polymer interactions: A review of progress in understanding polymer resist mask durability during plasma etching for nanoscale fabrication

Abstract: Photolithographic patterning of organic materials and plasma-based transfer of photoresist patterns into other materials have been remarkably successful in enabling the production of nanometer scale devices in various industries. These processes involve exposure of highly sensitive polymeric nanostructures to energetic particle fluxes that can greatly alter surface and near-surface properties of polymers. The extension of lithographic approaches to nanoscale technology also increasingly involves organic mask patterns produced using soft lithography, block copolymer self-assembly, and extreme ultraviolet lithographic techniques. In each case, an organic film-based image is produced, which is subsequently transferred by plasma etching techniques into underlying films/substrates to produce nanoscale materials templates. The demand for nanometer scale resolution of image transfer protocols requires understanding and control of plasma/organic mask interactions to a degree that has not been achieved. For manufa...