Hiroshi Kano

Bio: Hiroshi Kano is an academic researcher from Sony Broadcast & Professional Research Laboratories. The author has contributed to research in topics: Magnetization & Magnetoresistance. The author has an hindex of 17, co-authored 100 publications receiving 2363 citations.

A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram

Abstract: A novel nonvolatile memory utilizing spin torque transfer magnetization switching (STS), abbreviated spin-RAM hereafter, is presented for the first time The spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM This new programming mode has been accomplished owing to our tailored MTJ, which has an oval shape of 100 times 150 nm The memory cell is based on a 1-transistor and a 1-MTJ (ITU) structure The 4kbit spin-RAM was fabricated on a 4 level metal, 018 mum CMOS process In this work, writing speed as high as 2 ns, and a write current as low as 200 muA were successfully demonstrated It has been proved that spin-RAM possesses outstanding characteristics such as high speed, low power and high scalability for the next generation universal memory

Storage element and memory

Abstract: A storage element including a storage layer configured to hold information by use of a magnetization state of a magnetic material, with a pinned magnetization layer being provided on one side of the storage layer, with a tunnel insulation layer, and with the direction of magnetization of the storage layer being changed through injection of spin polarized electrons by passing a current in the lamination direction, so as to record information in the storage layer, wherein a spin barrier layer configured to restrain diffusion of the spin polarized electrons is provided on the side, opposite to the pinned magnetization layer, of the storage layer; and the spin barrier layer includes at least one material selected from the group composing of oxides, nitrides, and fluorides.

Magnetoresistive effect element and magnetic memory device

Abstract: A magnetoresistive effect element may be given satisfactory magnetic characteristics because a deterioration of a magnetoresistive changing rate by annealing can be suppressed and a magnetic memory device includes this magnetoresistive effect element to provide excellent write characteristics. A magnetoresistive effect element has a pair of ferromagnetic layers (magnetization fixed layer 5 and magnetization free layer 7 ) opposed to each other through an intermediate layer 6 to cause an electric current to flow in the direction perpendicular to the layer surface to obtain a magnetoresistive change. A magnetic memory device comprises the magnetoresistive effect element 1 in which at least one of the pair of ferromagnetic layers 5, 7 contains an amorphous ferromagnetic material whose crystallization temperature is higher than 623 K and bit lines and word lines sandwiching this magnetoresistive effect element and the magnetoresistive effect element in the thickness direction.

Memory device and memory

Abstract: A memory device is provided. The memory device includes a memory layer and a fixed-magnetization layer. The memory layer retains information based on a magnetization state of a magnetic material. The fixed-magnetization layer is formed on the memory layer through an intermediate layer made of an insulating material. The information is recorded on the memory layer with a change in a magnetization direction of the memory layer caused by injecting a spin-polarized electron in a stacked direction. A level of effective demagnetizing field, which is received by the memory layer, is smaller than a saturation-magnetization level of magnetization of the memory layer.

Substrate temperature effect on giant magnetoresistance of sputtered Co/Cu multilayers

Abstract: The relation between giant magnetoresistance (GMR) and the substrate temperature was investigated in sputtered Co/Cu multilayers. The magnetoresistance (MR) ratio is increased as the substrate temperature is decreased. The increase in the MR ratio is considered to be caused by the improvement in the sharpness of interfaces as concluded from the satellite peak intensity of the x‐ray diffraction. The rough interfaces reduce the antiferromagnetic coupled areas and result in the MR ratio decrease. By lowering the substrate temperature to 20 °C, the MR ratio of 80% at room temperature was obtained.

A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction

Abstract: Magnetic tunnel junctions (MTJs) with ferromagnetic electrodes possessing a perpendicular magnetic easy axis are of great interest as they have a potential for realizing next-generation high-density non-volatile memory and logic chips with high thermal stability and low critical current for current-induced magnetization switching. To attain perpendicular anisotropy, a number of material systems have been explored as electrodes, which include rare-earth/transition-metal alloys, L1(0)-ordered (Co, Fe)-Pt alloys and Co/(Pd, Pt) multilayers. However, none of them so far satisfy high thermal stability at reduced dimension, low-current current-induced magnetization switching and high tunnel magnetoresistance ratio all at the same time. Here, we use interfacial perpendicular anisotropy between the ferromagnetic electrodes and the tunnel barrier of the MTJ by employing the material combination of CoFeB-MgO, a system widely adopted to produce a giant tunnel magnetoresistance ratio in MTJs with in-plane anisotropy. This approach requires no material other than those used in conventional in-plane-anisotropy MTJs. The perpendicular MTJs consisting of Ta/CoFeB/MgO/CoFeB/Ta show a high tunnel magnetoresistance ratio, over 120%, high thermal stability at dimension as low as 40 nm diameter and a low switching current of 49 microA.

The emergence of spin electronics in data storage

Abstract: Electrons have a charge and a spin, but until recently these were considered separately. In classical electronics, charges are moved by electric fields to transmit information and are stored in a capacitor to save it. In magnetic recording, magnetic fields have been used to read or write the information stored on the magnetization, which 'measures' the local orientation of spins in ferromagnets. The picture started to change in 1988, when the discovery of giant magnetoresistance opened the way to efficient control of charge transport through magnetization. The recent expansion of hard-disk recording owes much to this development. We are starting to see a new paradigm where magnetization dynamics and charge currents act on each other in nanostructured artificial materials. Ultimately, 'spin currents' could even replace charge currents for the transfer and treatment of information, allowing faster, low-energy operations: spin electronics is on its way.

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

Abstract: Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.

A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram

Abstract: A novel nonvolatile memory utilizing spin torque transfer magnetization switching (STS), abbreviated spin-RAM hereafter, is presented for the first time The spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM This new programming mode has been accomplished owing to our tailored MTJ, which has an oval shape of 100 times 150 nm The memory cell is based on a 1-transistor and a 1-MTJ (ITU) structure The 4kbit spin-RAM was fabricated on a 4 level metal, 018 mum CMOS process In this work, writing speed as high as 2 ns, and a write current as low as 200 muA were successfully demonstrated It has been proved that spin-RAM possesses outstanding characteristics such as high speed, low power and high scalability for the next generation universal memory

Phase change memory technology

Abstract: The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...