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Author

Hisanori Ihara

Other affiliations: Samsung, Hiroshima University
Bio: Hisanori Ihara is an academic researcher from Toshiba. The author has contributed to research in topics: Amorphous silicon & Layer (electronics). The author has an hindex of 11, co-authored 41 publications receiving 371 citations. Previous affiliations of Hisanori Ihara include Samsung & Hiroshima University.

Papers
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Patent
19 Mar 1998
TL;DR: In this article, the problem of ejection of a signal charge at a signal accumulating part and to prevent deterioration of dynamic range in an element, thermal noise, residual image, etc., in the dark from generating, even when the pixel size of a MOS type solidstate image pick up device is reduced, a read gate voltage is deteriorated and a well concentration is increased.
Abstract: PROBLEM TO BE SOLVED: To facilitate ejection of a signal charge at a signal accumulating part and to prevent deterioration of dynamic range in an element, thermal noise, residual image, etc., in the dark from generating, even when the pixel size of a MOS type solid-state image pick up device is reduced, a read gate voltage is deteriorated and a well concentration is increased. SOLUTION: On the surface of a p-type silicon substrate 21, a (p) + type diffusion layer 23 which constitutes a photoelectric conversion region 22 and the drain 24 of a read MOS type field effect transistor are formed. At the lower part of the (p) + diffusion layer 23, a signal accumulating part 25 formed of an (n) type diffusion layer is formed adjacent to the (p) + type diffusion layer. On the surface of the silicon substrate 21, the gate electrode 26 of a MOS type field effect transistor is provided between the (p) + diffusion layer 23 and the drain 24. The edge part of the gate electrode 26 of the MOS transistor of the signal accumulating part 25 is protruded, having its edge position extended downward from the read gate electrode 26 of the diffusion layer 23 further than the edge part of the read gate electrode 26 of the (p) + diffusion layer 23 provided on the surface of the silicon substrate 21. COPYRIGHT: (C)1999,JPO

49 citations

Patent
久典 井原1, Hisanori Ihara
18 Feb 2015
TL;DR: In this article, an image sensor of the present invention includes a substrate that has a first and a second surface facing the first surface and receiving light incident thereon, and defines a plurality of pixel regions.
Abstract: PROBLEM TO BE SOLVED: To provide an image sensor capable of improving dark current characteristics, and a method of fabricating the image sensor.SOLUTION: An image sensor of the present invention includes a substrate that has a first surface and a second surface facing the first surface and receiving light incident thereon, and defines a plurality of pixel regions. The substrate having the second surface receiving light incident thereon defines a deep trench extending in a direction from the second surface toward the first surface and separating the plurality of pixel regions from each other. In each of the pixel regions, a photoelectric conversion part is disposed. A gate electrode is disposed on the photoelectric conversion part, and a negative fixed charge film covering the second surface and at least a portion of a sidewall of the deep trench is provided. The image sensor further includes a shallow element isolation layer disposed on the first surface of the substrate. The shallow element isolation film defines an active region in each of the pixel regions and is in contact with the negative fixed charge film.

35 citations

Patent
29 Oct 2002
TL;DR: In this article, a photoelectric conversion unit is used to reduce a color mixture or a dark current induced by an inflow of signal charge from an adjacent photodiode in a solid-state image sensing device.
Abstract: PROBLEM TO BE SOLVED: To provide a solid-state image sensing device which is capable of reducing a color mixture or a dark current induced by an inflow of signal charge from an adjacent photodiode SOLUTION: The solid-state image sensing device is equipped with a plurality of photoelectric conversion units which are each composed of a first conductivity-type first semiconductor region 201 and a second conductivity-type second semiconductor region 203 formed inside the first semiconductor region 201, and a gate electrode 205 which is formed on the surface of the first semiconductor region 201 through the intermediary of a gate insulating film 206 Furthermore, a first conductivity-type barrier region 204 higher in impurity concentration than the first semiconductor region 201 is formed inside the surface of the first semiconductor region 201 in the lower region of the second semiconductor region 203 included in the selected photoelectric conversion units COPYRIGHT: (C)2004,JPO

24 citations

Journal ArticleDOI
TL;DR: In this paper, the defect density at the i/p interface is reduced by H2 plasma treatment of the interface, and the performance of a-Si:H diodes is improved by this treatment.
Abstract: Hydrogenated amorphous silicon (a-Si:H) n-i-p diodes in which the intrinsic (i-type) layer surfaces were exposed to an H2 plasma before depositing the p-type layer (H2 plasma treatment of the i/p interface) were prepared. The effects of this H2 plasma treatment of the i/p interface were observed by dark I-V, photo-I-V under 450 nm illumination, and quasistatic C-V measurements. It has been found that the defect density at the i/p interface is reduced by this treatment. It has also been determined that the performance of a-Si:H diodes is improved by this treatment of the interface.

22 citations

Patent
14 Jul 1997
TL;DR: In this article, the problem of increasing photoelectric conversion gain in a unit cell to obtain the high sensitivity of a solid-state image sensing device and suppress bursting-in of noise from a vertical signal conductor or the like to make the realization of low noise possible is solved.
Abstract: PROBLEM TO BE SOLVED: To increase a photoelectric conversion gain in a unit cell to obtain the high sensitivity of a solid-state image sensing device and also to suppress bursting-in of noise from a vertical signal conductor or the like to make the realization of low noise possible. SOLUTION: Gate wirings 23 and 24 of first and second readout transistors and a drain 25 of the first readout transistor are formed between first and second diodes 21 and 22 on an element region 20. This drain 25 is connected with a gate 27 of an amplitude transistor via a jump wiring 26. Thus gate 27 of the amplitude transistor is connected also with a source 31, which is formed on an element region 30 of a reset transistor, of the reset transistor via the wiring 26. The source 31 and a drain 33 on the opposite side to the source 31 are formed holding a gate wiring 32 of the reset transistor between them on the region 30 of the above reset transistor.

22 citations


Cited by
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Patent
28 Jan 2004
TL;DR: In this article, a distance image sensor for removing the background light and improving the charge transfer efficiency in a device for measuring the distance to an object by measuring the time-of-flight of the light.
Abstract: A distance image sensor for removing the background light and improving the charge transfer efficiency in a device for measuring the distance to an object by measuring the time-of-flight of the light. In a distance image sensor for determining the signals of two charge storage nodes which depend on the delay time of the modulated light, a signal by the background light is received from the third charge storage node or the two charge storage nodes in a period when the modulated light does not exist, and is subtracted from the signal which depends on the delay time of the two charge storage nodes, so as to remove the influence of the background. Also by using a buried diode as a photo-detector, and using an MOS gate as gate means, the charge transfer efficiency improves. The charge transfer efficiency is also improved by using a negative feedback amplifier where a capacitor is disposed between the input and output.

353 citations

Patent
Yuichiro Yamashita1
10 Nov 2010
TL;DR: In this article, a solid-state imaging apparatus which performs a global exposure operation, in a determined imaging region, for performing exposure as matching respective start times and respective end times of all rows, comprises: plural unit pixels arranged in two-dimensional matrix and each comprising a photoelectric converting unit for generating a pixel signal by photoelectric conversion, a holding unit for holding the generated pixel signal, and a first gate for transferring the generated signal to the holding unit; a vertical controlling circuit for resetting the unit pixel; and an first driving line connected to the first controlling line, and
Abstract: A solid-state imaging apparatus which performs a global exposure operation, in a determined imaging region, for performing exposure as matching respective start times and respective end times of all rows, comprises: plural unit pixels arranged in two-dimensional matrix and each comprising a photoelectric converting unit for generating a pixel signal by photoelectric conversion, a holding unit for holding the generated pixel signal, and a first gate for transferring the generated pixel signal to the holding unit; a first controlling line connected commonly to the first gates in the unit pixels on the same row; a vertical controlling circuit for resetting the unit pixel; and a first driving line connected to the first controlling line, and not connected to and thus independent of the vertical controlling circuit, thereby enabling to reduce a current flowing in a power supply of the vertical controlling circuit when driving electrodes of the holding units.

217 citations

Patent
06 Jan 2014
TL;DR: In this paper, the shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistor shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the column direction.
Abstract: A solid-state imaging device includes a pixel region in which shared pixels which share pixel transistors in a plurality of photoelectric conversion portions are two-dimensionally arranged. The shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistors shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the shared pixels are arranged along the column direction.

141 citations

Patent
30 Nov 2001
TL;DR: In this article, an integrated color pixel (ICP) with at least one integrated metal filter is presented, where the wavelength responsivity is specified and integrated at pixel level into the ICP itself using metal materials already available for standard integrated circuit design and fabrication process.
Abstract: An integrated color pixel (ICP) with at least one integrated metal filter is presented. Rather than utilizing a separate color filter, the wavelength responsivity of the ICP is specified and integrated at pixel level into the ICP itself using metal materials already available for standard integrated circuit design and fabrication process. The ICP of the present invention is thus distinguished from a conventional color pixel constructed in a two-stage process that combines an image sensor with a color filter array or other optical material.

128 citations