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Author

Hisashi Kino

Bio: Hisashi Kino is an academic researcher from Tohoku University. The author has contributed to research in topics: Wafer & Flip chip. The author has an hindex of 11, co-authored 91 publications receiving 521 citations.


Papers
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Proceedings ArticleDOI
01 Dec 2010
TL;DR: In this article, a local tensile strain amount to 1.8 GPa was induced by 4×4 µm2 square sized Si microbumps in 10 µm-thick LSI wafers after bonding and curing.
Abstract: Mechanical strain/stress and crystal defects are produced in extremely thin wafers (thickness ∼10 µm) of 3D-LSIs not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density microbumps and curing. Furthermore, the metal of through-Si via (TSV) and microbump not only becomes the cause of contamination, but also induces strain/stress (due to the difference in the co-efficient of thermal expansion (CTE) between Si and metal) in thinned Si substrate. X-ray photoelectron spectroscopy (XPS) results showed that the crystal quality of Si is highly deteriorated in the ultra-poly ground (UPG) surface after wafer thinning and stress relief. Micro-Raman spectroscopy (µRS) data revealed that a local tensile strain amount to 1.8 GPa was induced by 4×4 µm2 square sized Si microbumps in 10 µm-thick LSI wafers after bonding and curing. We have noticed that this locally induced strain/stress caused more than 10% change in the ON current of p-MOS transistor. CuSn microbumps have also induced strain/stress at Si wafer surface, and it penetrates deeper for larger bump size and wider for smaller bump pitch.

75 citations

Proceedings ArticleDOI
01 Dec 2008
TL;DR: In this paper, the authors proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method.
Abstract: We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum were electrically connected by unique lateral interconnections formed crossing over chip edges with large step height. We evaluated fundamental electrical characteristics using daisy chains formed crossing over test chips which were face-up bonded onto the substrates by the self-assembly. We obtained excellent characteristics in these daisy chains. In addition, RF test chips with amplitude shift keying (ASK) demodulator and signal processing circuits were self-assembled onto the substrates and electrically connected by the lateral interconnections. We confirmed that these test chips work well.

48 citations

Proceedings ArticleDOI
01 Dec 2009
TL;DR: In this paper, the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated by micro-Raman spectroscopy (µRS) and XPS.
Abstract: Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (µRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor.

39 citations

Proceedings ArticleDOI
01 Dec 2011
TL;DR: In this paper, the authors proposed to increase the TSV pitch to larger than twice of TSV size to avoid these adverse effects in high density 3D-LSI, and ultra-small size In-Au μ-bump technology has been developed to minimize the influences of μ-bumps on device characteristics.
Abstract: High density 3D LSI technology using W/Cu hybrid through silicon vias (TSVs) has been proposed. Major reliability issues attributed to W/Cu hybrid TSVs in high density 3D LSIs such as (i) thermo-mechanical stress exerted by W TSVs used for signal lines and Cu TSVs used for power/ground lines in active Si, (ii) external gettering (EG) role played by sub-surface defects in thinned Si substrate, and (iii) effect of local stress induced by μ-bumps on device characteristics are discussed. By annealing at the temperature of ≥300°C, both Cu (via size ≤10µm) and W (via size ≤1µm) square TSVs induce only compressive stress at small TSV spacing which will seriously affect the mobility in active Si area, and thus device characteristics. Large compressive stress not only leads to extrusion and peeling of TSV metal, but also die cracking, and it will adversely impact on the reliability of 3D-LSIs. Then it was proposed to increase the TSV pitch to larger than twice of TSV size to avoid these adverse effects in high density 3D-LSI. Sub-surface defects at dry polished (DP) surface well act as potential EG sites for Cu contamination. Influences of mechanical stress induced by μ-bumps on device characteristics were also evaluated and ultra-small size In-Au μ-bump technology has been developed to minimize the influences of μ-bumps on device characteristics.

39 citations

Journal ArticleDOI
TL;DR: In this paper, a reconfigured wafer-to-wafer 3-D integration is proposed, where many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer.
Abstract: A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.

35 citations


Cited by
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Journal Article
TL;DR: In this paper, an archaeal light-driven chloride pump (NpHR) was developed for temporally precise optical inhibition of neural activity, allowing either knockout of single action potentials, or sustained blockade of spiking.
Abstract: Our understanding of the cellular implementation of systems-level neural processes like action, thought and emotion has been limited by the availability of tools to interrogate specific classes of neural cells within intact, living brain tissue. Here we identify and develop an archaeal light-driven chloride pump (NpHR) from Natronomonas pharaonis for temporally precise optical inhibition of neural activity. NpHR allows either knockout of single action potentials, or sustained blockade of spiking. NpHR is compatible with ChR2, the previous optical excitation technology we have described, in that the two opposing probes operate at similar light powers but with well-separated action spectra. NpHR, like ChR2, functions in mammals without exogenous cofactors, and the two probes can be integrated with calcium imaging in mammalian brain tissue for bidirectional optical modulation and readout of neural activity. Likewise, NpHR and ChR2 can be targeted together to Caenorhabditis elegans muscle and cholinergic motor neurons to control locomotion bidirectionally. NpHR and ChR2 form a complete system for multimodal, high-speed, genetically targeted, all-optical interrogation of living neural circuits.

1,520 citations

01 Jan 2007
TL;DR: Bit-Cost Scalable (BiCS) technology is proposed which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost.
Abstract: We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

152 citations

Journal ArticleDOI
TL;DR: In this article, the state-of-the-art of wafer-level heterogeneous integration technologies suitable for MOEMS, MEMS, and NEMS devices are reviewed.
Abstract: Wafer-level heterogeneous integration technologies for microoptoelectromechanical systems (MOEMS), microelectromechanical systems (MEMS), and nanoelectromechanical systems (NEMS) enable the combination of dissimilar classes of materials and components into single systems. Thus, high-performance materials and subsystems can be combined in ways that would otherwise not be possible, and thereby forming complex and highly integrated micro- or nanosystems. Examples include the integration of high-performance optical, electrical or mechanical materials such as monocrystalline silicon, graphene or III-V materials with integrated electronic circuits. In this paper the state-of-the-art of wafer-level heterogeneous integration technologies suitable for MOEMS, MEMS, and NEMS devices are reviewed. Various heterogeneous MOEMS, MEMS, and NEMS devices that have been described in literature are presented.

132 citations

Journal ArticleDOI
Koshi Takenaka1
TL;DR: In this paper, the authors classify and review mechanisms and materials of NTE to suggest means of improving their functionality and of developing new materials, and present some recent activities related to how these giant NTE materials are used as practical thermal expansion compensators.
Abstract: To meet strong demands for the control of thermal expansion necessary because of the advanced development of industrial technology, widely various giant negative thermal expansion (NTE) materials have been developed during the last decade. Discovery of large isotropic NTE in ZrW2O8 has greatly advanced research on NTE deriving from its characteristic crystal structure, which is now classified as conventional NTE. Materials classified in this category have increased rapidly. In addition to development of conventional NTE materials, remarkable progress has been made in phase-transition-type NTE materials using a phase transition accompanied by volume contraction upon heating. These giant NTE materials have brought a paradigm shift in the control of thermal expansion. This report classifies and reviews mechanisms and materials of NTE to suggest means of improving their functionality and of developing new materials. A subsequent summary presents some recent activities related to how these giant NTE materials are used as practical thermal expansion compensators, with some examples of composites containing these NTE materials.

128 citations