Hoda Amer

Bio: Hoda Amer is an academic researcher from College of Information Technology. The author has contributed to research in topics: Reliability (statistics) & Electronic design automation. The author has an hindex of 3, co-authored 6 publications receiving 32 citations.

How much input vectors affect nano-circuit's reliability estimates

Abstract: As the sizes of (nano-)devices are aggressively scaled deep towards the nanometer range, the design and manufacturing of future (nano-)circuits will become extremely complex and inevitably introduce more defects, while their functioning will be adversely affected by (transient) faults. Therefore, accurately calculating the reliability of future designs will become a very important factor for (nano-)circuit designers as they investigate several alternatives for optimizing the tradeoffs between the conflicting metrics of area-power-energy-delay versus reliability. This paper studies the effect of the input vectors on the (nano-)circuit's reliability, and introduces a time-efficient method for quickly and accurately identifying the lower/upper reliability bounds. Simulations results support the claim that the absolute difference between the lowest and the highest achievable reliability is of one-to-two orders of magnitude. Therefore, future designs should consider the worst case input vector(s) in order to guarantee the required reliability margins.

Why should we care about input vectors

Abstract: As the size of future (nano-)devices is aggressively scaled deep into the nanometer range, the design and manufacturing of future (nano-)circuits will become extremely complex and inevitably introduce more defects and transient faults. Therefore, accurately calculating the reliability of future designs will become a very important factor for (nano-)circuit designers. This paper investigates the relationship between input vectors and the reliability of the output signal. The paper introduces the critical gate concept and highlights their effects on the circuit's reliability. Simulation results show that the circuit's reliability depends heavily on the status and location of the critical gates.

A Bayesian based EDA tool for accurate VLSI reliability evaluations

Abstract: As the sizes of (nano) device are aggressively scaled deep towards the nanometer regime, the design and manufacturing of future nano-circuits will become extremely complex and inevitably introduce more defects and their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important factor for nano-circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of area-power-energy-delay versus reliability. This paper introduces a novel EDA tool for accurate calculation of future nano-circuits reliabilities. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for comparing the reliability of different design alternatives, and for selecting the design that best fits a set of given (design) constraints.

An Affordable System for Remotely Monitoring Water Quality in Residential Water Tanks

Abstract: Water is an essential human need. In July 2010, the United Nations General Assembly explicitly recognized the human right to water and sanitation and acknowledged that clean drinking water and sanitation are essential to the realization of all human rights. Contaminated water does not only taste bad, it could be deadly. Water-related diseases affect more than 1.5 billion people every year. Unfortunately, there is limited awareness of the possibility of contamination in the residential water tanks, and more should be done to educate consumers on the importance of maintaining a hygienic water tank. In this paper a system is proposed to remotely sense, record, and report the quality of drinking water stored in residential tanks. The system sends alert messages to the landlord and the local authorities (if required) when one of the quality parameter is lower than the standard values.

Using Bayesian Networks to Accurately Calculate the Reliability of Complementary Metal Oxide Semiconductor Gates

Abstract: Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very successfully over the last four decades to improve the performance and the functionality of very large scale integrated (VLSI) designs. Still, scaling is heading towards several fundamental limits as the feature size is being decreased towards 10 nm and less. One of the challenges associated with scaling is the expected increase of static and dynamic parameter fluctuations and variations, as well as intrinsic and extrinsic noises, with significant effects on reliability. Therefore, there is a clear, growing need for electronic design automation (EDA) tools that can predict the reliability of future massive nano-scaled designs with very high accuracy. Such tools are essential to help VLSI designers optimize the conflicting tradeoffs between area-power-delay and reliability requirements. In this paper, we introduce an EDA tool that quickly and accurately estimates the reliability of any CMOS gate. The tool improves the accuracy of the reliability calculation at the gate level by taking into consideration the gate's topology, the reliability of the individual devices, the applied input vector, as well as the noise margins. It can also be used to estimate the effect on different types of faults and defects, and to estimate the effects of enhancing the reliability of individual devices on the gate's overall reliability.

On the Reliability of Computational Structures Using Majority Logic

Abstract: The importance of the reliability of majority-based structures stems from their use in both conventional fault-tolerant architectures and emerging nanoelectronic systems. In this paper, analytical models are developed in order to gain a better understanding of the reliability of majority logic in these contexts. A minimally biased input scenario for N-input majority gates ( N odd) occurs when only a minimal majority of the inputs are in consensus. In a tree of gates with these inputs, this paper determines 1) that any nonzero error rate of the majority gates and/or of its initial inputs will result in an unreliable output and 2) that the use of majority gates with a larger number of inputs leads to a less reliable structure. These results are extended to N-input minority gates for odd N. Although these findings are based on tree structures, their implications to circuit design are explored by investigating several fault-tolerant and nanoelectronic architectures. The simulation results show that the increased probability of error in nanoscale devices may impose serious constraints on the reliability of emerging nanoelectronic circuits, as well as their fault-tolerant counterparts. The worst case reliability must be accounted for in a fault-tolerant design to ensure reliable operation.

GREDA: A Fast and More Accurate Gate Reliability EDA Tool

Abstract: Generic as well as customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate the reliability of both present and future (nano)circuits. However, the accuracy of many of these EDA tools is questionable as they: 1) either assume that all gates have the same constant probability of failure (PFGATE=const.) , or 2) use very simple approaches to estimate the reliability of the elementary gates. In this paper, we introduce a gate reliability EDA tool (GREDA) that is able to estimate more accurately the reliability of CMOS gates by considering: 1) the gate's topology; 2) the variable probability of failure of the individual devices (PFDEV); 3) the applied input vector; 4) the reliability of the input signals; and 5) the input voltage variations (which can be linked to the allowed noise margins). GREDA can be used to calculate PFGATE due to different types of faults and/or defects, and to estimate the effects of enhancing PFDEV on PFGATE. Simulation results show that GREDA can improve on the accuracy of reliability calculations at the gate level.

Devices and Input Vectors are Shaping von Neumann Multiplexing

Abstract: This paper starts by reviewing many of the gate-level reliability analyses of von Neumann multiplexing (vN-MUX). It goes on to detail very accurate device-level (CMOS technology specific) analyses of vN-MUX with respect to threshold voltage variations, taking into account both the gates' topology as well as the input vectors. Such results are essential for a clear understanding of vN-MUX when considering the unreliable behavior of future nanodevices. These analyses should change the “view from the top” as revealing a different picture from the well-known gate-level theoretical and simulation results. The findings presented here are also able to explain certain apparently abnormal behaviors of vN-MUX reported based on Monte Carlo simulations, and should have implications for the appraisal and the design of future fault-tolerant nanoarchitectures.

Reliability of NAND-2 CMOS gates from threshold voltage variations

Abstract: The high-level approach for estimating circuit reliability tends to consider the probability of failure of a logic gate as a constant, and work towards the higher levels. With scaling, such gate-centric approaches become highly inaccurate, as both transistors and input vectors drastically affect the probability of failure of the logic gates. This paper will present a transistor-level gate failure analysis starting from threshold voltage variations. We will briefly review the state-of-the-art, and rely upon freshly reported results for threshold voltage variations. These will be used to estimate the probabilities of failure of a classical NAND-2 CMOS gate for (a few) different technologies, voltages, and input vectors. They will also reveal huge differences between the highest and the lowest probabilities of failure, and will show how strongly these are affected by the supply voltage.